From patchwork Sat Apr 9 04:17:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 559233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D4BAC433FE for ; Sat, 9 Apr 2022 04:17:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240751AbiDIETX (ORCPT ); Sat, 9 Apr 2022 00:19:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240743AbiDIETX (ORCPT ); Sat, 9 Apr 2022 00:19:23 -0400 Received: from mail-40130.protonmail.ch (mail-40130.protonmail.ch [185.70.40.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF23BD95C7; Fri, 8 Apr 2022 21:17:16 -0700 (PDT) Date: Sat, 09 Apr 2022 04:17:08 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail; t=1649477834; bh=gC2D3uYjVBhkCwgNw3OoZdjOU5tGxtwsCPqWNVYkFgE=; h=Date:To:From:Cc:Reply-To:Subject:Message-ID:From:To:Cc:Date: Subject:Reply-To:Feedback-ID:Message-ID; b=AYENJ+zBJklbKWilpmUGy1KcZs+MxUUWqGGGqabR8SaWcdxdy2qBDWrSuu7ViKXjs O8+M7VUxNaYsdvm2QKtTl5Je+axEHBM1EZ8fewvJi5EQ8gh7/h5BBT7K1aewcYXH53 jQY0qIYlY80NZmVMCvt4mrduVSVRUqHYsvoI0+cIRVwMoub08/1jYC3jUNlgksZSSj U110Cd2V1H4rF8XRTlWhCgTw0gg4fdU/vLDuMejMaUcs1ZmZydoH1OeIVNfqjXJQSi 3pfga3mEmbcfpO9ls5KhlzzDh0GFDFB9g4PKjNF25gHtKcawjiCx1SgMLFkbdMRksJ nMaP73Py5TV5Q== To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" From: Yassine Oudjana Cc: Yassine Oudjana , Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Reply-To: Yassine Oudjana Subject: [PATCH v2 4/9] cpufreq: qcom_cpufreq_nvmem: Simplify reading kryo speedbin Message-ID: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org MSM8996 and MSM8996 Pro have different OPPs with different dependencies on CPR and CBF levels. Sharing the same OPP tables will make implementing CPR and CBF scaling quite difficult, as it will become necessary to use opp-supported-hw not only to choose CPU OPPs, but to also choose their required CPR and CBF OPPs which are different on the same CPU OPP between MSM8996 and MSM8996 Pro. The best solution would be to make a new device tree for MSM8996 Pro which would override the OPP tables from the existing MSM8996 device tree. In preparation for adding a separate device tree for MSM8996 Pro, skip reading msm-id from smem and just read the speedbin efuse. Signed-off-by: Yassine Oudjana --- drivers/cpufreq/Kconfig.arm | 1 - drivers/cpufreq/qcom-cpufreq-nvmem.c | 75 +++------------------------- 2 files changed, 6 insertions(+), 70 deletions(-) -- 2.35.1 diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 954749afb5fe..7d9798bc5753 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -154,7 +154,6 @@ config ARM_QCOM_CPUFREQ_NVMEM tristate "Qualcomm nvmem based CPUFreq" depends on ARCH_QCOM depends on QCOM_QFPROM - depends on QCOM_SMEM select PM_OPP help This adds the CPUFreq driver for Qualcomm Kryo SoC based boards. diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 6dfa86971a75..a2b895a930cb 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -9,8 +9,8 @@ * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables * defines the voltage and frequency value based on the msm-id in SMEM * and speedbin blown in the efuse combination. - * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC - * to provide the OPP framework with required information. + * The qcom-cpufreq-nvmem driver reads efuse value from the SoC to provide the + * OPP framework with required information. * This is used to determine the voltage and frequency value for each OPP of * operating-points-v2 table when it is parsed by the OPP framework. */ @@ -27,22 +27,6 @@ #include #include #include -#include - -#define MSM_ID_SMEM 137 - -enum _msm_id { - MSM8996V3 = 0xF6ul, - APQ8096V3 = 0x123ul, - MSM8996SG = 0x131ul, - APQ8096SG = 0x138ul, -}; - -enum _msm8996_version { - MSM8996_V3, - MSM8996_SG, - NUM_OF_MSM8996_VERSIONS, -}; struct qcom_cpufreq_drv; @@ -142,35 +126,6 @@ static void get_krait_bin_format_b(struct device *cpu_dev, dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver); } -static enum _msm8996_version qcom_cpufreq_get_msm_id(void) -{ - size_t len; - u32 *msm_id; - enum _msm8996_version version; - - msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len); - if (IS_ERR(msm_id)) - return NUM_OF_MSM8996_VERSIONS; - - /* The first 4 bytes are format, next to them is the actual msm-id */ - msm_id++; - - switch ((enum _msm_id)*msm_id) { - case MSM8996V3: - case APQ8096V3: - version = MSM8996_V3; - break; - case MSM8996SG: - case APQ8096SG: - version = MSM8996_SG; - break; - default: - version = NUM_OF_MSM8996_VERSIONS; - } - - return version; -} - static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, struct nvmem_cell *speedbin_nvmem, char **pvs_name, @@ -178,30 +133,13 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, { size_t len; u8 *speedbin; - enum _msm8996_version msm8996_version; *pvs_name = NULL; - msm8996_version = qcom_cpufreq_get_msm_id(); - if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { - dev_err(cpu_dev, "Not Snapdragon 820/821!"); - return -ENODEV; - } - speedbin = nvmem_cell_read(speedbin_nvmem, &len); if (IS_ERR(speedbin)) return PTR_ERR(speedbin); - switch (msm8996_version) { - case MSM8996_V3: - drv->versions = 1 << (unsigned int)(*speedbin); - break; - case MSM8996_SG: - drv->versions = 1 << ((unsigned int)(*speedbin) + 4); - break; - default: - BUG(); - break; - } + drv->versions = 1 << (unsigned int)(*speedbin); kfree(speedbin); return 0; @@ -464,10 +402,9 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list); /* - * Since the driver depends on smem and nvmem drivers, which may - * return EPROBE_DEFER, all the real activity is done in the probe, - * which may be defered as well. The init here is only registering - * the driver and the platform device. + * Since the driver depends on the nvmem driver, which may return EPROBE_DEFER, + * all the real activity is done in the probe, which may be defered as well. + * The init here is only registering the driver and the platform device. */ static int __init qcom_cpufreq_init(void) {