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[209.132.180.67]) by mx.google.com with ESMTP id d12-v6si5653422plr.442.2018.02.12.03.03.41; Mon, 12 Feb 2018 03:03:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=NUkPfz8X; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933722AbeBLLDk (ORCPT + 10 others); Mon, 12 Feb 2018 06:03:40 -0500 Received: from mail-qk0-f195.google.com ([209.85.220.195]:33971 "EHLO mail-qk0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933494AbeBLLDj (ORCPT ); Mon, 12 Feb 2018 06:03:39 -0500 Received: by mail-qk0-f195.google.com with SMTP id o7so3496164qkc.1 for ; Mon, 12 Feb 2018 03:03:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=RzH3xSnepQwfMU9Mn0h5xUaXC/1Wyi2PiONumPTL79Y=; b=NUkPfz8XA2lAs2LF2u04sALx3jrSZQP9LanhSsCGth7GLc7oqz0icdb2Y+lmE9XdfG xFvTECXoBQSY9/I+0fflOC2NpiKwhLl5JAAvwHFiGDrY7PRVOAAJcrmvM4Y48wrjZHZd Z07lCo29pJipoMFLXTOfkjhfCrFLt823GrivM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=RzH3xSnepQwfMU9Mn0h5xUaXC/1Wyi2PiONumPTL79Y=; b=oRZKOaCyJ8EtNx7rFiDGZp626a/JSgeZ49jnF+a9Ls/C6mxUP8AebWcx7ZTRuHGj73 hpwFRpTCsE/l8z0th/IC4U4BPB0HGQQUPgzReTLJQj9ehXd0mitolhqGHqCUfXUGrMeo LK6C3VgjUtYThAQF0xtjZiyXZO5wH+jl7PFDkOkW+ESneZzemPwDOOgLvEgubjx2D6QF tYH11vBSq/kGc8FpNsw/QuFgP7TumbOxmWe1ZU9tbxwpKk/TMWKHL2PZa5OnUWQX40vN G/lhBWZ2HqkJXNJXYHps7mIjvZdi8W7oRsndROhTYiIl22IDO40F43DGIPhT+cR7riLR waCg== X-Gm-Message-State: APf1xPD78fzVjEQDeJiTHw21mNwRxPPRa72Z/BUfNdJa/5U3L21bTVNH oZj79Ju30yz6zIpYwDNBiMkvAg== X-Received: by 10.55.133.71 with SMTP id h68mr16187551qkd.106.1518433418750; Mon, 12 Feb 2018 03:03:38 -0800 (PST) Received: from localhost ([49.248.181.160]) by smtp.gmail.com with ESMTPSA id l36sm6168140qte.55.2018.02.12.03.03.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Feb 2018 03:03:38 -0800 (PST) From: Amit Kucheria To: andy.gross@linaro.org Cc: linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, Catalin Marinas , Will Deacon , Arnd Bergmann , Gregory CLEMENT , Timur Tabi , Wei Xu , Alex Elder , Rob Herring , Heiko Stuebner , Krzysztof Kozlowski , Ard Biesheuvel , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: defconfig: Enable the APCS IPC driver on Qualcomm platforms Date: Mon, 12 Feb 2018 16:33:32 +0530 Message-Id: <6ab84c75aadc152fdd7c63282ee6690096b8b704.1518415510.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The APCS block is present on several Qualcomm SoCs e.g. 8916, 8996. On the 8916 it is needed to enable the clock controller that in turn enables cpufreq on the platform while on the 8996 it is needed for communication with RPM. Signed-off-by: Amit Kucheria --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Bjorn Andersson diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 634b373..96a8ed8 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -525,6 +525,7 @@ CONFIG_ARM_MHU=y CONFIG_PLATFORM_MHU=y CONFIG_BCM2835_MBOX=y CONFIG_HI6220_MBOX=y +CONFIG_QCOM_APCS_IPC=y CONFIG_ROCKCHIP_IOMMU=y CONFIG_ARM_SMMU=y CONFIG_ARM_SMMU_V3=y