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[209.132.180.67]) by mx.google.com with ESMTP id ly10si30577297pab.211.2014.08.20.01.06.49 for ; Wed, 20 Aug 2014 01:06:50 -0700 (PDT) Received-SPF: none (google.com: devicetree-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751528AbaHTIGc (ORCPT + 6 others); Wed, 20 Aug 2014 04:06:32 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:54826 "EHLO mail-pa0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751494AbaHTIGa (ORCPT ); Wed, 20 Aug 2014 04:06:30 -0400 Received: by mail-pa0-f45.google.com with SMTP id eu11so11786247pac.4 for ; Wed, 20 Aug 2014 01:06:27 -0700 (PDT) X-Received: by 10.70.37.134 with SMTP id y6mr57016506pdj.33.1408521986321; Wed, 20 Aug 2014 01:06:26 -0700 (PDT) Received: from [192.168.1.4] ([117.198.93.65]) by mx.google.com with ESMTPSA id t5sm21579071pbs.4.2014.08.20.01.06.20 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 20 Aug 2014 01:06:24 -0700 (PDT) Message-ID: <53F456F3.3000309@linaro.org> Date: Wed, 20 Aug 2014 09:06:11 +0100 From: Srinivas Kandagatla User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 To: "Ivan T. Ivanov" , Linus Walleij , Grant Likely , Rob Herring CC: Bjorn Andersson , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 2/6] pinctrl: Introduce pinctrl driver for Qualcomm SSBI PMIC's References: <1407771634-14946-1-git-send-email-iivanov@mm-sol.com> <1407771634-14946-3-git-send-email-iivanov@mm-sol.com> In-Reply-To: <1407771634-14946-3-git-send-email-iivanov@mm-sol.com> Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: srinivas.kandagatla@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Hi Bjorn, Two things which I noticed while trying out this driver to drive a reset line. 1> gpio numbering for pinconf vs gpio are not consistent, they differ by an offset of 1. For example to control GPIO43 I had to do something like this in pinconf: wlan_default_gpios: wlan-gpios { pios { pins = "gpio43"; function = "normal"; bias-disable; power-source = ; }; }; for same pin for gpio I had to do: reset-gpio = <&pm8921_gpio 42 GPIO_ACTIVE_LOW>; This offset by 1 is bit confusing and can easily lead to errors which are hard to find. I think this should be easy to fix.. 2> Looking back at v3.4 kernel, for gpio modes, BIT(0) of bank 0 is set to enable gpio mode. without this bit driver does not work for output pins. here is the patch which fixes this: From 5a5c5171a3371cf38ccd157922ea140bfd0253d5 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 20 Aug 2014 07:18:03 +0100 Subject: [PATCH] pinctrl:qcom:ssbi: Enable gpio mode Looking back at 3.4 kernel driver, it looks like the gpio enable bit is missing in this driver. This patch is just a hack to get the wlan reset line working. Signed-off-by: Srinivas Kandagatla --- drivers/pinctrl/qcom/pinctrl-ssbi-pmic.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) val = pin->direction << 2; diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-pmic.c b/drivers/pinctrl/qcom/pinctrl-ssbi-pmic.c index 27e5ec9..2633ea1 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-pmic.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-pmic.c @@ -49,6 +49,7 @@ #define SSBI_REG_ADDR_GPIO_BASE 0x150 #define SSBI_REG_ADDR_GPIO(n) (SSBI_REG_ADDR_GPIO_BASE + n) +#define PM8XXX_GPIO_MODE_ENABLE BIT(0) #define PM8XXX_GPIO_WRITE BIT(7) #define PM8XXX_MAX_GPIOS 44 @@ -493,7 +494,8 @@ static int pm8xxx_gpio_config_set(struct pinctrl_dev *pctldev, } if (banks & BIT(0)) - pm8xxx_gpio_write(pctrl, offset, 0, pin->power_source << 1); + pm8xxx_gpio_write(pctrl, offset, 0, pin->power_source << 1 | + PM8XXX_GPIO_MODE_ENABLE); if (banks & BIT(1)) {