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[209.132.180.67]) by mx.google.com with ESMTP id s24si4396224plq.41.2018.11.27.08.30.08; Tue, 27 Nov 2018 08:30:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GN32gwz6; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731107AbeK1D2P (ORCPT + 15 others); Tue, 27 Nov 2018 22:28:15 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:36979 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730613AbeK1D2P (ORCPT ); Tue, 27 Nov 2018 22:28:15 -0500 Received: by mail-wr1-f65.google.com with SMTP id j10so23355920wru.4 for ; Tue, 27 Nov 2018 08:29:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=ySS9ak8736GKuz1GUi70Wz4dUI9Ax/bqLZ13e7Wb3I8=; b=GN32gwz6a40w4VNUMQAm1giD/L8kZ0ljSCYaGM8U0EDH+IVi+geVy5+tuQgmwZJOB8 CWvstXEIiz5PbxNq3qrCiy/0lcx5jhfrC8mZRSdnPgEYSzydQUIdH9Jap12PpR/vFLw2 GITimkipCpZmMumNmuqSgpMV6aIp77E4GALTM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=ySS9ak8736GKuz1GUi70Wz4dUI9Ax/bqLZ13e7Wb3I8=; b=OoGhrtADJT0QLR3whrbJJcrODDWRSsx8Xet0NgsZ244BerMNzuTWlPQ/fIkqxmdGaX 8NjBCbt3OELVdxTYnqA0H6dlzRefBaWPzMqyKYs+v0bDBrL4UufNIvdoB1qa2QqFG0NB qrQtWoO9KZt9YifZibT6Ac1/Tgaft9D/EHofT+J34yXhkYjhLDBubsZoQrIJlD5iM/Ms bw5003Uai0K/juYcQb+aGjidyLk1N6PfKtazsDQaWjOplpW5SduG4e3Ro/qznrkEeBlz 23aOGDYWXIKqJq5Np79p4D1C2Or+7Nht62ZXhUVPzveO/zGUzWTWkV+QK+2vtrpBqweC 56Rw== X-Gm-Message-State: AA+aEWbabhu1fuIo+eGrbRVPWKi9SNvIHq7nAkf9Api8LRH0L7JolPDh gvlQ9QI1UulE9Vcb/0bYhktcWw== X-Received: by 2002:adf:de91:: with SMTP id w17mr12831912wrl.320.1543336187565; Tue, 27 Nov 2018 08:29:47 -0800 (PST) Received: from localhost ([49.248.92.105]) by smtp.gmail.com with ESMTPSA id a1sm5158091wrw.76.2018.11.27.08.29.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Nov 2018 08:29:46 -0800 (PST) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, vkoul@kernel.org, khasim.mohammed@linaro.org, David Brown , Rob Herring , Mark Rutland Subject: [PATCH v3 3/4] arm64: dts: qcom: qcs404: Add tsens controller Date: Tue, 27 Nov 2018 21:59:06 +0530 Message-Id: <3491110ccf708efed795bfc756b2d108f8dbb710.1543335819.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org qcs404 has a single TSENS IP block with 10 sensors. The calibration data is stored in an eeprom (qfprom) that is accessed through the nvmem framework. We add the qfprom node to allow the tsens sensors to be calibrated correctly. Signed-off-by: Amit Kucheria Reviewed-by: Vinod Koul Tested-by: Vinod Koul --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 9b5c16562bbe..57d14d8f0c90 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -253,6 +253,16 @@ reg = <0x00060000 0x6000>; }; + qfprom: qfprom@a4000 { + compatible = "qcom,qfprom"; + reg = <0x000a4000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + tsens_caldata: caldata@d0 { + reg = <0x1f8 0x14>; + }; + }; + rng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>; @@ -260,6 +270,16 @@ clock-names = "core"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_caldata>; + nvmem-cell-names = "calib"; + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,qcs404-pinctrl"; reg = <0x01000000 0x200000>,