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[209.132.180.67]) by mx.google.com with ESMTP id b10-v6si574588pgi.416.2018.09.12.02.54.36; Wed, 12 Sep 2018 02:54:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CSmf9G95; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727968AbeILO6V (ORCPT + 13 others); Wed, 12 Sep 2018 10:58:21 -0400 Received: from mail-ed1-f68.google.com ([209.85.208.68]:34258 "EHLO mail-ed1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727957AbeILO6V (ORCPT ); Wed, 12 Sep 2018 10:58:21 -0400 Received: by mail-ed1-f68.google.com with SMTP id u1-v6so1278479eds.1 for ; Wed, 12 Sep 2018 02:54:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=DdplkWwuGrY04uo9ngGJyb9h118OGPlbF94r8PIE8s4=; b=CSmf9G958OeJacKZorMKFy+xTfe9oydbq9gNkUDPxEal8PbfyZIbPdS+kRrsaO6L9W hcgNfWG/KSkLOnbaAFEc3WEOCU6mew8ReFBr/J3Kz1VTe+N0GC1aAGrT7G9KJZNzg5GU rUTG8WJqrzg4xmXK3CpXlTfHE+FGN121H87gg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=DdplkWwuGrY04uo9ngGJyb9h118OGPlbF94r8PIE8s4=; b=Z7f6dlhHKNBBBjfFUxGG+uGmPoDOskjvsyLA/1VpR3l1b5iU/RkyQMqmuIwuqkxSsX xgKgVZ4bn60I0U/mJO5ahfv3x7R5mAUO5j0rlmjIgP9+/uU8CLTzvv5MUZgrzkbtYvYT xRxEc1TfX8yrzrhPnraZuuYf5m6n8eibtveaTzpDUXL+W8JOzV+QUCW/dG643FIbY38m iIVd3gauP8L0eeW2iJtLX/rg3Opsw005/1au0pJOAou0K4N8meb11OHpGnHN8kh+YFUG i/dBsft75G4VaY87S5paNQwUIymztQk1J+bibzhNAfcsIo9DP+m6F+Mq2CHrZQFRenqE SICA== X-Gm-Message-State: APzg51BtjGI/SLb0wFm5B/0fRuOepLGvNl+8i2hUZtFxp5WaIxBQVd8J o1V8mYh9SpTChJOwuiXX3XxBFw== X-Received: by 2002:a50:de8e:: with SMTP id c14-v6mr1757958edl.196.1536746073097; Wed, 12 Sep 2018 02:54:33 -0700 (PDT) Received: from localhost ([49.248.190.214]) by smtp.gmail.com with ESMTPSA id a19-v6sm482112edd.69.2018.09.12.02.54.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Sep 2018 02:54:32 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, smohanad@codeaurora.org, andy.gross@linaro.org, dianders@chromium.org, mka@chromium.org, David Brown , Rob Herring , Mark Rutland , linux-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 10/16] arm64: dts: msm8916: thermal: split address space into two Date: Wed, 12 Sep 2018 15:22:55 +0530 Message-Id: <226a3b61f23f27d54b4dad390d6796b429fad837.1536744310.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We've earlier added support to split the register address space into TM and SROT regions. Split up the regmap address space into two for msm8916 that has a similar register layout. Since tsens-common.c/init_common() currently only registers one address space, the order is important (TM before SROT). This is OK since the code doesn't really use the SROT functionality yet. Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 7b32b8990d62..6a277fce3333 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -761,9 +761,10 @@ }; }; - tsens: thermal-sensor@4a8000 { + tsens: thermal-sensor@4a9000 { compatible = "qcom,msm8916-tsens"; - reg = <0x4a8000 0x2000>; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; nvmem-cell-names = "calib", "calib_sel"; #thermal-sensor-cells = <1>;