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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-231d4e97886sm126652165ad.146.2025.05.23.12.07.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 May 2025 12:07:53 -0700 (PDT) From: Unnathi Chalicheemala Date: Fri, 23 May 2025 12:07:41 -0700 Subject: [PATCH v7 2/3] firmware: qcom_scm: Support multiple waitq contexts Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250523-multi_waitq_scm-v7-2-5b51b60ed396@oss.qualcomm.com> References: <20250523-multi_waitq_scm-v7-0-5b51b60ed396@oss.qualcomm.com> In-Reply-To: <20250523-multi_waitq_scm-v7-0-5b51b60ed396@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@oss.qualcomm.com, Prasad Sodagudi , Satya Durga Srinivasu Prabhala , Trilok Soni , Unnathi Chalicheemala X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748027270; l=4803; i=unnathi.chalicheemala@oss.qualcomm.com; s=20240514; h=from:subject:message-id; bh=ZykR5KDDu2LYLt2a2csTXDEitMti0SIv3lJ2U21A6qQ=; b=P46Xv/T44A/cvwXNPWe6Ei1xWLGgSpJCwLgOv5ujhXiP6o0nnF892rV25PyXeEVKJkfRLVyTr re1N6DwYdG7DFBCVDfFMUKXG8JyKL88q6c5BFHScH4lliEAx8754zdC X-Developer-Key: i=unnathi.chalicheemala@oss.qualcomm.com; a=ed25519; pk=o+hVng49r5k2Gc/f9xiwzvR3y1q4kwLOASwo+cFowXI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIzMDE3NCBTYWx0ZWRfX++4AKirU5IKL OaO0dCtJsTMh8wAFtVaEVSBiAZ/zIHQbbtGf8gUpYGyR60jY49oEUzLhRzQcAUDB/kica4YbBRt runncvNUWb4uHpz9fnjxLb8UkMC9UcFTjd6tN8ftUVZD2cBtYypiXbzbcebhwF1tA+jFZ3Cq7If CoDIp1SLLUHcmzkfuHxHn7bgJhvmNaITpge3iDoq80qizpacZF7z8K3Ov8sSuoC1x3O+VE0BB5v F3vZuSBOKEOkNps/5etjTrkXvooeRjdPa9BKAuwoc42OGLVcqiL5NzZd+yXs5gozcsYfpUK2RQa Z0+zZFeLJ1+CQafjZXJLKCdMWXAK5FEouxodw/qdI8ImfhD59CLCGWqjyySf+N1fJH+bRnIYwgQ C3dXJ8k2Q0MeoRMkR6iSYwUAFy5ilsxsUP2Z0Jckc+cW+01WWzHq6mzJLykjgXYV9vVLgbGi X-Authority-Analysis: v=2.4 cv=RIuzH5i+ c=1 sm=1 tr=0 ts=6830c78c cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=IoDWPEjDBkkTTY39AZoA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-ORIG-GUID: 67zxQL6kbWBcDXekt5wFiKRr4m1e9_rK X-Proofpoint-GUID: 67zxQL6kbWBcDXekt5wFiKRr4m1e9_rK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-23_06,2025-05-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 suspectscore=0 malwarescore=0 bulkscore=0 mlxlogscore=999 spamscore=0 lowpriorityscore=0 mlxscore=0 priorityscore=1501 adultscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505230174 Currently, only a single waitqueue context exists, with waitqueue id zero. Multi-waitqueue mechanism is added in firmware to support the case when multiple VMs make SMC calls or single VM making multiple calls on same CPU. When VMs make SMC call, firmware will allocate waitqueue context assuming the SMC call to be a blocking call. SMC calls that cannot acquire resources are returned to sleep in the calling VM. When resource is available, VM will be notified to wake sleeping thread and resume SMC call. SM8650 firmware can allocate two such waitq contexts so create these two waitqueue contexts. Unique waitqueue contexts are supported by a dynamically sized array where each unique wq_ctx is associated with a struct completion variable for easy lookup. To get the number of waitqueue contexts directly from firmware, qcom_scm_query_waitq_count() is introduced. On older targets which support only a single waitqueue, wq_cnt is set to 1 as SCM call for query_waitq_count() is not implemented for single waitqueue case. Signed-off-by: Unnathi Chalicheemala --- drivers/firmware/qcom/qcom_scm.c | 75 ++++++++++++++++++++++++++++------------ 1 file changed, 53 insertions(+), 22 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 529e1d067b1901c4417a1f1fd9c3255ee31de532..c2682e9bde58b6f132af0c1bc2e194db0e401e3b 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -47,7 +47,7 @@ struct qcom_scm { struct clk *iface_clk; struct clk *bus_clk; struct icc_path *path; - struct completion waitq_comp; + struct completion *waitq; struct reset_controller_dev reset; /* control access to the interconnect path */ @@ -57,6 +57,7 @@ struct qcom_scm { u64 dload_mode_addr; struct qcom_tzmem_pool *mempool; + unsigned int wq_cnt; }; struct qcom_scm_current_perm_info { @@ -2118,6 +2119,25 @@ static int qcom_scm_fill_irq_fwspec_params(struct irq_fwspec *fwspec, u32 virq) return 0; } +static int qcom_scm_query_waitq_count(struct qcom_scm *scm) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_WAITQ, + .cmd = QCOM_SCM_WAITQ_GET_INFO, + .owner = ARM_SMCCC_OWNER_SIP + }; + struct qcom_scm_res res; + + ret = qcom_scm_call_atomic(scm->dev, &desc, &res); + if (ret) { + dev_info(scm->dev, "Multi-waitqueue support unavailable\n"); + return ret; + } + + return res.result[0] & GENMASK(7, 0); +} + static int qcom_scm_get_waitq_irq(void) { int ret; @@ -2149,42 +2169,40 @@ static int qcom_scm_get_waitq_irq(void) return ret; } -static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx) +static struct completion *qcom_scm_get_completion(u32 wq_ctx) { - /* FW currently only supports a single wq_ctx (zero). - * TODO: Update this logic to include dynamic allocation and lookup of - * completion structs when FW supports more wq_ctx values. - */ - if (wq_ctx != 0) { - dev_err(__scm->dev, "Firmware unexpectedly passed non-zero wq_ctx\n"); - return -EINVAL; - } + struct completion *wq; - return 0; + if (WARN_ON_ONCE(wq_ctx >= __scm->wq_cnt)) + return ERR_PTR(-EINVAL); + + wq = &__scm->waitq[wq_ctx]; + + return wq; } int qcom_scm_wait_for_wq_completion(u32 wq_ctx) { - int ret; + struct completion *wq; - ret = qcom_scm_assert_valid_wq_ctx(wq_ctx); - if (ret) - return ret; + wq = qcom_scm_get_completion(wq_ctx); + if (IS_ERR(wq)) + return PTR_ERR(wq); - wait_for_completion(&__scm->waitq_comp); + wait_for_completion(wq); return 0; } static int qcom_scm_waitq_wakeup(unsigned int wq_ctx) { - int ret; + struct completion *wq; - ret = qcom_scm_assert_valid_wq_ctx(wq_ctx); - if (ret) - return ret; + wq = qcom_scm_get_completion(wq_ctx); + if (IS_ERR(wq)) + return PTR_ERR(wq); - complete(&__scm->waitq_comp); + complete(wq); return 0; } @@ -2260,6 +2278,7 @@ static int qcom_scm_probe(struct platform_device *pdev) struct qcom_tzmem_pool_config pool_config; struct qcom_scm *scm; int irq, ret; + int i; scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL); if (!scm) @@ -2270,7 +2289,19 @@ static int qcom_scm_probe(struct platform_device *pdev) if (ret < 0) return ret; - init_completion(&scm->waitq_comp); + ret = qcom_scm_query_waitq_count(scm); + if (ret < 0) + return ret; + + scm->wq_cnt = ret; + + scm->waitq = devm_kcalloc(&pdev->dev, scm->wq_cnt, sizeof(*scm->waitq), GFP_KERNEL); + if (!scm->waitq) + return -ENOMEM; + + for (i = 0; i < scm->wq_cnt; i++) + init_completion(&scm->waitq[i]); + mutex_init(&scm->scm_bw_lock); scm->path = devm_of_icc_get(&pdev->dev, NULL);