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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-550e703c2f3sm3482506e87.214.2025.05.22.12.03.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 May 2025 12:03:33 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 22 May 2025 22:03:20 +0300 Subject: [PATCH v5 01/30] drm/msm/dpu: stop passing mdss_ver to setup_timing_gen() Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250522-dpu-drop-features-v5-1-3b2085a07884@oss.qualcomm.com> References: <20250522-dpu-drop-features-v5-0-3b2085a07884@oss.qualcomm.com> In-Reply-To: <20250522-dpu-drop-features-v5-0-3b2085a07884@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: Neil Armstrong , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3775; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=/jtEB/eJ70Kwf3ZRDcLKCteC/8VDM7I/q74Ga6UWOgI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoL3T7fyavGriyaGHOj+ADxHUnLpxMPrK8HtV8i TMAZBo/dmCJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaC90+wAKCRCLPIo+Aiko 1Qz4B/9/zYYjE1ZBotnVsVpgFu835IeL57emvaCd5NC4Ll9kNPtZ75ai0PL8BIf+M8dgSffevtl giD8oXN1n5hVbBh5eAxH69ztZEBrI3AJeqgZcIl3D5WXln1EwAp0soeINMuIK5J3nQimMhUFyrM 5o3eW2+kOUrPNZ19nXL0dJt75xuzpBYt7BSOqeRPunxAIfoWLlfGryVXBWHkfKG98AwM2lxhrzs CUKjnMftbz06GQJKmtte2V6ZsULO9S/TXsj25REbt+X3vW/YoOULxSWIdwTLn7OdOmwqUl+5bKy 6qOvclVm+BrIJzR5vC7oicPCr5FHeV7vulPT27AC4EnTFh+L X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: 7AiIELTv2bIkWhP9CIrO2uJGRzcTGwqS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIyMDE5MSBTYWx0ZWRfX5qR7/EjlLird ckSUz+yxXB7R47SByeQ+4uIpoUkYSy5A7APZk9tNIrFKKCz6ytYyKetd640yLXw1u2azfxOfZhu 8sCZDoFVPcIhVn28Y/tszhVQG6G2oVRww1W1F//8S6tr9qwxKxAyG2IK6XzfUA7Zr/HVP6YBSeH Tdg/smUiGfmK2YhsqWSVBAQFsITgZ+r6eA/tGEk5pbvuTsFA3mLvT2LJf5JR3abZ9TKm5+rouoZ XTxp5KGLXuTjT9HFriwZZNbpfod6JzAQM6plytZ9FqWNzHCExRM3l35rNqLwNU03MnEsMmhllCr LrlhBNNu01SuZ/uR7y7z/G6DjYzcJhtV+qyip14etu7qX1rem2QdvLboeqx2x9N6QBXknsX4Chi IV+MjdS8S3ySwyvRLVtDeAdFyMogsC5qk0zCN+SRp7pXqvZX6vPoxQ96Q9zyh16q3n9Mq2mw X-Authority-Analysis: v=2.4 cv=fZOty1QF c=1 sm=1 tr=0 ts=682f7507 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=Fc1Z5Xec4v_XsjI5eh8A:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 7AiIELTv2bIkWhP9CIrO2uJGRzcTGwqS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-22_09,2025-05-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 adultscore=0 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505220191 From: Dmitry Baryshkov As a preparation to further MDSS-revision cleanups stop passing MDSS revision to the setup_timing_gen() callback. Instead store a pointer to it inside struct dpu_hw_intf and use it diretly. It's not that the MDSS revision can chance between dpu_hw_intf_init() and dpu_encoder_phys_vid_setup_timing_engine(). Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 3 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 7 ++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 5 +++-- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 8a618841e3ea89acfe4a42d48319a6c54a1b3495..d35d15b60260037c5c0c369cb061e7759243b6fd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -309,8 +309,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, - &timing_params, fmt, - phys_enc->dpu_kms->catalog->mdss_ver); + &timing_params, fmt); phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); /* setup which pp blk will connect to this intf */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index fb1d25baa518057e74fec3406faffd48969d492b..1d56c21ac79095ab515aeb485346e1eb5793c260 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -98,8 +98,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, const struct dpu_hw_intf_timing_params *p, - const struct msm_format *fmt, - const struct dpu_mdss_version *mdss_ver) + const struct msm_format *fmt) { struct dpu_hw_blk_reg_map *c = &intf->hw; u32 hsync_period, vsync_period; @@ -180,7 +179,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */ if (p->compression_en && !dp_intf && - mdss_ver->core_major_ver >= 7) + intf->mdss_ver->core_major_ver >= 7) intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; hsync_data_start_x = hsync_start_x; @@ -580,6 +579,8 @@ struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev, c->idx = cfg->id; c->cap = cfg; + c->mdss_ver = mdss_rev; + c->ops.setup_timing_gen = dpu_hw_intf_setup_timing_engine; c->ops.setup_prg_fetch = dpu_hw_intf_setup_prg_fetch; c->ops.get_status = dpu_hw_intf_get_status; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index 114be272ac0ae67fe0d4dfc0c117baa4106f77c9..f31067a9aaf1d6b96c77157135122e5e8bccb7c4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -81,8 +81,7 @@ struct dpu_hw_intf_cmd_mode_cfg { struct dpu_hw_intf_ops { void (*setup_timing_gen)(struct dpu_hw_intf *intf, const struct dpu_hw_intf_timing_params *p, - const struct msm_format *fmt, - const struct dpu_mdss_version *mdss_ver); + const struct msm_format *fmt); void (*setup_prg_fetch)(struct dpu_hw_intf *intf, const struct dpu_hw_intf_prog_fetch *fetch); @@ -126,6 +125,8 @@ struct dpu_hw_intf { enum dpu_intf idx; const struct dpu_intf_cfg *cap; + const struct dpu_mdss_version *mdss_ver; + /* ops */ struct dpu_hw_intf_ops ops; };