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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-328084ca34csm14186881fa.30.2025.05.18.04.21.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 May 2025 04:21:41 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 18 May 2025 14:21:35 +0300 Subject: [PATCH v6 02/11] drm/msm/dp: read hw revision only once Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250518-fd-dp-audio-fixup-v6-2-2f0ec3ec000d@oss.qualcomm.com> References: <20250518-fd-dp-audio-fixup-v6-0-2f0ec3ec000d@oss.qualcomm.com> In-Reply-To: <20250518-fd-dp-audio-fixup-v6-0-2f0ec3ec000d@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Paloma Arellano Cc: Douglas Anderson , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4182; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=ZQK3De9spKq2bOT0Hl1HvbbvggyGKbTI3+3PIdSsFLY=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoKcK/Hs1HGodxey0UOVjoJO2Kl/jlINR9/hl6O 1fkgwO0m2uJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaCnCvwAKCRCLPIo+Aiko 1bqIB/0eR7M7/nrB8bKHxc+BHj/vguTWWbNuciMREsFKLdHnJ/NIus2916NlmOCHfEJPEvfVJar C/pV5dShhMJjpHX39OlauTv7EZQZ7UIm44O65CFA9sEC8B9JHHOhCvXlb0xlMeyPWLW8Wx66iRw apc6bhIUYJEHeGULbtNEjYYQosy9kByMe8om9Q5U301UhXL7T0Xs78xe803YpHUMNvPTfkNHqTe edgTO/2iqUEtZcKixGT8AhmZtvxHEjc0wpEUiKQDeDZ94KzhB4GvYTvJmtQAfnSOOsQEjhdSwkT EtlO3kZhj4hBiHirJscN9TtudorIJw5Zc0SEEnX2e/79S5Ak X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE4MDEwOCBTYWx0ZWRfX31X/0bsna8hN fWVdjkVCrHvkzPaV/bCXwOLjZ2JONzZAjzgqD0c2B3Qf/be8fpHpCgpQdb8ui1ZyBfcQt4kj0bf bl7oxF7DsA/XB8+tAo8q6YhAgtHQI4Qu4D7RRhtk1Q6nvZFKJ4/6LHAirhNv/doYUzTZdilpBbJ Yz6Y4YThsN0NJoqiuOK1IdopQbsfDRnIffG8q7TXEf2JUfQiBG+j/+j6gkjWQFRP/vnySIqb2pW Qns9v9GPpo5ZQmNZV25W6Hc4qEFBejBYWwusfUEBQOBQFyjn5qnCdar4UFPAG8XEByz12CiPhCC A1OXbB8YT2105sG8zmKM3JGSPCWug3HJCB+1I6WSnGYr5Mrbrqo6dbOHpeTqH9ixDTly1mtXOiu 1ctF0VMBaMyrmJJuwsQuWpfPxFPgRbLBJvs0k6FAfzDmNGQNVYioRuI3yuN1SUV4MbJ8uKqB X-Proofpoint-ORIG-GUID: wH2o_KWPOOU_S1OdCv4YY_ISPGizkAVr X-Authority-Analysis: v=2.4 cv=PpyTbxM3 c=1 sm=1 tr=0 ts=6829c2c8 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=cm27Pg_UAAAA:8 a=pC6Btxr2GG0oDPZGBtIA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: wH2o_KWPOOU_S1OdCv4YY_ISPGizkAVr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-18_06,2025-05-16_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 mlxscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 phishscore=0 bulkscore=0 impostorscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505180108 From: Dmitry Baryshkov There is little point in rereading DP controller revision over and over again. Read it once, after the first software reset. Reviewed-by: Stephen Boyd Tested-by: Stephen Boyd # sc7180-trogdor Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_catalog.c | 29 ++++++++--------------------- drivers/gpu/drm/msm/dp/dp_catalog.h | 2 +- 2 files changed, 9 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 4f80eceb6ae19f542110d7379007f57c2ac16a8a..23f9fcb75123a58b3a4b69d3dad0598135108eec 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -414,14 +414,13 @@ void msm_dp_catalog_ctrl_config_misc(struct msm_dp_catalog *msm_dp_catalog, void msm_dp_catalog_setup_peripheral_flush(struct msm_dp_catalog *msm_dp_catalog) { - u32 mainlink_ctrl, hw_revision; + u32 mainlink_ctrl; struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); mainlink_ctrl = msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); - hw_revision = msm_dp_catalog_hw_revision(msm_dp_catalog); - if (hw_revision >= DP_HW_VERSION_1_2) + if (msm_dp_catalog->hw_revision >= DP_HW_VERSION_1_2) mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; else mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; @@ -514,22 +513,6 @@ int msm_dp_catalog_ctrl_set_pattern_state_bit(struct msm_dp_catalog *msm_dp_cata return 0; } -/** - * msm_dp_catalog_hw_revision() - retrieve DP hw revision - * - * @msm_dp_catalog: DP catalog structure - * - * Return: DP controller hw revision - * - */ -u32 msm_dp_catalog_hw_revision(const struct msm_dp_catalog *msm_dp_catalog) -{ - const struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - return msm_dp_read_ahb(catalog, REG_DP_HW_VERSION); -} - /** * msm_dp_catalog_ctrl_reset() - reset DP controller * @@ -556,6 +539,9 @@ void msm_dp_catalog_ctrl_reset(struct msm_dp_catalog *msm_dp_catalog) sw_reset &= ~DP_SW_RESET; msm_dp_write_ahb(catalog, REG_DP_SW_RESET, sw_reset); + + if (!msm_dp_catalog->hw_revision) + msm_dp_catalog->hw_revision = msm_dp_read_ahb(catalog, REG_DP_HW_VERSION); } bool msm_dp_catalog_ctrl_mainlink_ready(struct msm_dp_catalog *msm_dp_catalog) @@ -895,9 +881,10 @@ static void msm_dp_catalog_panel_update_sdp(struct msm_dp_catalog *msm_dp_catalo u32 hw_revision; catalog = container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); + hw_revision = msm_dp_catalog->hw_revision; - hw_revision = msm_dp_catalog_hw_revision(msm_dp_catalog); - if (hw_revision < DP_HW_VERSION_1_2 && hw_revision >= DP_HW_VERSION_1_0) { + if (hw_revision < DP_HW_VERSION_1_2 && + hw_revision >= DP_HW_VERSION_1_0) { msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x01); msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x00); } diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h index 08bb42e91b779633875dbeb4130bc55a6571cfb1..379fa4fef9ceb63b20c4aec2fca1e09003dc738b 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -33,6 +33,7 @@ struct msm_dp_catalog { bool wide_bus_en; + u32 hw_revision; }; /* Debug module */ @@ -61,7 +62,6 @@ void msm_dp_catalog_ctrl_config_misc(struct msm_dp_catalog *msm_dp_catalog, u32 void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catalog *msm_dp_catalog, u32 rate, u32 stream_rate_khz, bool is_ycbcr_420); int msm_dp_catalog_ctrl_set_pattern_state_bit(struct msm_dp_catalog *msm_dp_catalog, u32 pattern); -u32 msm_dp_catalog_hw_revision(const struct msm_dp_catalog *msm_dp_catalog); void msm_dp_catalog_ctrl_reset(struct msm_dp_catalog *msm_dp_catalog); bool msm_dp_catalog_ctrl_mainlink_ready(struct msm_dp_catalog *msm_dp_catalog); void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog, bool enable);