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Wed, 14 May 2025 19:09:49 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 14 May 2025 12:09:43 -0700 From: Jagadeesh Kona Date: Thu, 15 May 2025 00:38:51 +0530 Subject: [PATCH v4 06/18] clk: qcom: common: Add support to configure clk regs in qcom_cc_really_probe Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250515-videocc-pll-multi-pd-voting-v4-6-571c63297d01@quicinc.com> References: <20250515-videocc-pll-multi-pd-voting-v4-0-571c63297d01@quicinc.com> In-Reply-To: <20250515-videocc-pll-multi-pd-voting-v4-0-571c63297d01@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Vladimir Zapolskiy" , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: S_px0ft6E-bXeFT9pUj0qMoqPc4zXDae X-Proofpoint-ORIG-GUID: S_px0ft6E-bXeFT9pUj0qMoqPc4zXDae X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDE3NCBTYWx0ZWRfX3zU7xvEOgdiA nbitdFOTLSxVDlHeNQn6HP8QlczIfAZHvBHHmOesOeJ/uqgT6A3yf7muHup1dHC7AhaR2FUEgma fzlTjSs5VaCtlUDU7IAajIXaLrFu3WHpz/J8kOdd4b10HOPBoYADat+yMcOzWvW/5zngHwWKUMv Wr10okG03CPmQoN+uNsTyBKdsKYS5hpkeM//hUPXNh2vwGh0RSaz4Jc1JTcw+rMqHhi3JKmO8FZ pgxGbHgLrAxrSfQo5JhuhdadwptYoLUwOhNZBdSBVHfR9ejsz0CB4Niq3oSjYZYUrUz/aJRRRZK o/sobCXzOFGl/7f757KjXnyUMA94dfUtl6IK3O3OJnYlDcIZe9x9m+6huNn45dns2n6d5EwALds c7+iDA93hfVAjIOMVPM5T2PWxggz0P9uphqc9D08lfTNQqOYKULN6odCR2uqGJBObIHDionH X-Authority-Analysis: v=2.4 cv=LOFmQIW9 c=1 sm=1 tr=0 ts=6824ea7e cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=VTlJxEOIkQDSKMlf4IcA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_04,2025-05-14_03,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 adultscore=0 priorityscore=1501 suspectscore=0 mlxscore=0 malwarescore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 clxscore=1015 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505140174 Add support to configure PLLS and clk registers in qcom_cc_really_probe(). This ensures all required power domains are enabled and kept ON by runtime PM code in qcom_cc_really_probe() before configuring the PLLS or clock registers. Add support for qcom_cc_driver_data struct to maintain the clock controllers PLLs and CBCRs data, and a pointer of it can be stored in clock descriptor structure. If any clock controller driver requires to program some additional misc register settings, it can register the clk_regs_configure() callback in the driver data. Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/common.c | 39 +++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/common.h | 9 +++++++++ 2 files changed, 48 insertions(+) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 9cbf1c5296dad3ee5477a2f5a445488707663b9d..3b86d4953c3d90fd679ad38390279f0c1e37258f 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -14,6 +14,8 @@ #include #include "common.h" +#include "clk-alpha-pll.h" +#include "clk-branch.h" #include "clk-rcg.h" #include "clk-regmap.h" #include "reset.h" @@ -285,6 +287,38 @@ static int qcom_cc_icc_register(struct device *dev, desc->num_icc_hws, icd); } +static void qcom_cc_clk_pll_configure(const struct qcom_cc_driver_data *data, + struct regmap *regmap) +{ + const struct clk_init_data *init; + struct clk_alpha_pll *pll; + int i; + + for (i = 0; i < data->num_alpha_plls; i++) { + pll = data->alpha_plls[i]; + init = pll->clkr.hw.init; + + if (!pll->config || !pll->regs) { + pr_err("%s: missing pll config or regs\n", init->name); + continue; + } + + qcom_clk_alpha_pll_configure(pll, regmap); + } +} + +static void qcom_cc_clk_regs_configure(struct device *dev, const struct qcom_cc_driver_data *data, + struct regmap *regmap) +{ + int i; + + for (i = 0; i < data->num_clk_cbcrs; i++) + qcom_branch_set_clk_en(regmap, data->clk_cbcrs[i]); + + if (data->clk_regs_configure) + data->clk_regs_configure(dev, regmap); +} + int qcom_cc_really_probe(struct device *dev, const struct qcom_cc_desc *desc, struct regmap *regmap) { @@ -315,6 +349,11 @@ int qcom_cc_really_probe(struct device *dev, return ret; } + if (desc->driver_data) { + qcom_cc_clk_pll_configure(desc->driver_data, regmap); + qcom_cc_clk_regs_configure(dev, desc->driver_data, regmap); + } + reset = &cc->reset; reset->rcdev.of_node = dev->of_node; reset->rcdev.ops = &qcom_reset_ops; diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h index 9c10bc8c197cd7dfa25ccd245763ad6acb081523..0f4b2d40c65cf94de694226f63ca30f4181d0ce5 100644 --- a/drivers/clk/qcom/common.h +++ b/drivers/clk/qcom/common.h @@ -25,6 +25,14 @@ struct qcom_icc_hws_data { int clk_id; }; +struct qcom_cc_driver_data { + struct clk_alpha_pll **alpha_plls; + size_t num_alpha_plls; + u32 *clk_cbcrs; + size_t num_clk_cbcrs; + void (*clk_regs_configure)(struct device *dev, struct regmap *regmap); +}; + struct qcom_cc_desc { const struct regmap_config *config; struct clk_regmap **clks; @@ -39,6 +47,7 @@ struct qcom_cc_desc { size_t num_icc_hws; unsigned int icc_first_node_id; bool use_rpm; + struct qcom_cc_driver_data *driver_data; }; /**