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Wed, 14 May 2025 19:09:32 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 14 May 2025 12:09:26 -0700 From: Jagadeesh Kona Date: Thu, 15 May 2025 00:38:48 +0530 Subject: [PATCH v4 03/18] dt-bindings: clock: qcom: sm8450-camcc: Allow to specify two power domains Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250515-videocc-pll-multi-pd-voting-v4-3-571c63297d01@quicinc.com> References: <20250515-videocc-pll-multi-pd-voting-v4-0-571c63297d01@quicinc.com> In-Reply-To: <20250515-videocc-pll-multi-pd-voting-v4-0-571c63297d01@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Vladimir Zapolskiy" , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 3owEy3VjoxPGQuUS08dklE8t2iPLSdZw X-Proofpoint-ORIG-GUID: 3owEy3VjoxPGQuUS08dklE8t2iPLSdZw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDE3NCBTYWx0ZWRfXyjfd4rCtNcTn B5M+cRCzSQZxEMMm0W3yR2Sr2QUgzsi3s5nRQ8sPgIOA703l6+/KRZLxVt4w7FrSEiS8pPRExsE plGaM7lpd3BYJWAnkIrpDGJqpff6/vosL3Dxq//3Q8r4X6iIgRVv/pt7Gc/3ufkYrBn5oIU92AC FTDcoRHyMrxLrkb1jtmVkuoQ+SKmUXp80SQvvqFtXoxj/C0rhNA/XQyMrkB9YSHwTF9+6auqdxA 2M+VahQs8i2+IUgfkBuAkV2TvNZV/M3S3QaMGukM5gTwv8ieOUC1t2pxtmE+zT0AAFvioO1fugK fixXP/mrJFQlNXD3Je7Zizv5yMkjFOPWTwtKgO7C8BZt2X5ivq7QRMlHlW351EI8NnSYuThGAPO 9snAyR2tuxqgcnwoR+7k/z1Pq0AYYOcfbGmEvI5iGsiqoBYB5/aqPp+9zfzt/jRw0QlzMmZV X-Authority-Analysis: v=2.4 cv=KcvSsRYD c=1 sm=1 tr=0 ts=6824ea6d cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=VNckzqIK-Xfz9zBCpKcA:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_04,2025-05-14_03,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 clxscore=1015 adultscore=0 phishscore=0 lowpriorityscore=0 mlxlogscore=981 spamscore=0 malwarescore=0 impostorscore=0 mlxscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505140174 From: Vladimir Zapolskiy To configure the camera PLLs and enable the camera GDSCs on SM8450, SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along with MMCX. Therefore, update the camcc bindings to include the MXC power domain on these platforms. Fixes: 9cbc64745fc6 ("dt-bindings: clock: qcom: Add SM8550 camera clock controller") Signed-off-by: Vladimir Zapolskiy Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bryan O'Donoghue Signed-off-by: Jagadeesh Kona --- .../devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index 883f12e3d11fa16384108434f6de120162226a28..c1e06f39431e68a3cd2f6c2dba84be2a3c143bb1 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -35,14 +35,18 @@ properties: - description: Sleep clock source power-domains: - maxItems: 1 description: - A phandle and PM domain specifier for the MMCX power domain. + Power domains required for the clock controller to operate + items: + - description: MMCX power domain + - description: MXC power domain required-opps: - maxItems: 1 description: - A phandle to an OPP node describing required MMCX performance point. + OPP nodes that describe required performance points on power domains + items: + - description: MMCX performance point + - description: MXC performance point reg: maxItems: 1 @@ -80,8 +84,10 @@ examples: <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;