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Wed, 14 May 2025 19:10:36 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 14 May 2025 12:10:30 -0700 From: Jagadeesh Kona Date: Thu, 15 May 2025 00:38:59 +0530 Subject: [PATCH v4 14/18] arm64: dts: qcom: sm8550: Additionally manage MXC power domain in videocc Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250515-videocc-pll-multi-pd-voting-v4-14-571c63297d01@quicinc.com> References: <20250515-videocc-pll-multi-pd-voting-v4-0-571c63297d01@quicinc.com> In-Reply-To: <20250515-videocc-pll-multi-pd-voting-v4-0-571c63297d01@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Vladimir Zapolskiy" , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ifWXVrus-BGRA_wgAOa-hO9DbDn4boxS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDE3NCBTYWx0ZWRfX2p6iXazZPnlR N2oZRM99HcDbl/aaZAqHRSOYC3BycBFoPbZprls1NjHIQk35oHV7gRkp3oIBxcyuWFZo1ksSdfg 3NzZLzemLIgBB4TfPRRvr8Zrbb6WC8r998Yl15lXRgBRYHIwTZaFhc8x117iYmDesZ2xSSLWaIK h5/CjoII46NLGeq8vdyGp4OQQZ1S8t/nKLtDbxE48BgX9bJpPt8p7pXqunp7MEB+QhE2dsFdCim qe2UbCZh3pZB58UTT1AFVZ0ej+mJPQPaOYwNaDWzJRZ0SQJpT6tNCCkymm7cAKoKaa69aegqnNc 1C3BX9TmZ74RCL87ZtLhBp4QhfTChfZm6n3fqY262VyhCFjbKJ4zGk8puxUvPYAmCstg6P6DQW3 fFLYAE9jzOVjPv+p56YC07bxzY/0TUYHszWi/3KJtipbafJ5EOBSLNRI/SwH9ixX/YoQEX6e X-Authority-Analysis: v=2.4 cv=K7UiHzWI c=1 sm=1 tr=0 ts=6824eaad cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=yDpTXWEf0LF08gPbhRgA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: ifWXVrus-BGRA_wgAOa-hO9DbDn4boxS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_04,2025-05-14_03,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 malwarescore=0 phishscore=0 mlxlogscore=582 clxscore=1015 bulkscore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505140174 Videocc requires both MMCX and MXC rails to be powered ON to configure the video PLLs on SM8550 platform. Hence add MXC power domain to videocc node on SM8550. Signed-off-by: Jagadeesh Kona Reviewed-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index f78d5292c5dd5ec88c8deb0ca6e5078511ac52b7..92017caedbbbea12eb2e43f2e9f5bcad0c0ee40c 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3225,8 +3225,10 @@ videocc: clock-controller@aaf0000 { reg = <0 0x0aaf0000 0 0x10000>; clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;