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Wed, 14 May 2025 19:09:20 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 14 May 2025 12:09:14 -0700 From: Jagadeesh Kona Date: Thu, 15 May 2025 00:38:46 +0530 Subject: [PATCH v4 01/18] dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250515-videocc-pll-multi-pd-voting-v4-1-571c63297d01@quicinc.com> References: <20250515-videocc-pll-multi-pd-voting-v4-0-571c63297d01@quicinc.com> In-Reply-To: <20250515-videocc-pll-multi-pd-voting-v4-0-571c63297d01@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Vladimir Zapolskiy" , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: SWL4503BsVpqlkn3s9OUTfHT_KLF0k9M X-Authority-Analysis: v=2.4 cv=HZ4UTjE8 c=1 sm=1 tr=0 ts=6824ea61 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=VwQbUJbxAAAA:8 a=Nwh09rWfvR_xP5f7LFwA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: SWL4503BsVpqlkn3s9OUTfHT_KLF0k9M X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDE3NCBTYWx0ZWRfX1d14hfWS0iWR Gzdo10RkkDAQosBNDZrtas9V3nyo0DrXMFanLL4BZFs6O0433Tgt1DVx67HYqCfw3LynN9V7Ajv OcvBOWAnRzEBuIO9P4WaYownREdy25dxn7MHxrMxbZFVe/NVEX/CPzaZWScPWmidPRWcIgt4LJr xJGRFVYPRGllURjJqniKJNHD0BPv4Qyv6A24fmX7WsPj+I7rKJtJ3ub4KRJhY+CkMUJL5fGFsNa yjBqzvEJhOeAqMpCzzaX+3wkCEzgUhuxo6he8sFToKJF3TKVixtlQhf3L9QFo7ubjmn0U4Hpz1M Se1CH4gvQZza9Sa3uumt8sOaMzL4cteYEyc+5+aKsr7b2se1spjweGzZS63FybbAj1pHxE3Dt3v bFNpxniBFhEp3UrO2DS9/oVV7KWl/YbGyEYjbCIniYDoLEo1BInZHJOAVBFuUURdXNREYgul X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_04,2025-05-14_03,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 spamscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 mlxscore=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 bulkscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505140174 To configure the video PLLs and enable the video GDSCs on SM8450, SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along with MMCX. Therefore, update the videocc bindings to include the MXC power domain on these platforms. Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller") Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index 62714fa54db82491a7a108f7f18a253d737f8d61..0d99178332cb99d3f02f50605e19b9b26e3ec807 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -32,14 +32,18 @@ properties: - description: Video AHB clock from GCC power-domains: - maxItems: 1 description: - MMCX power domain. + Power domains required for the clock controller to operate + items: + - description: MMCX power domain + - description: MXC power domain required-opps: - maxItems: 1 description: - A phandle to an OPP node describing required MMCX performance point. + OPP nodes that describe required performance points on power domains + items: + - description: MMCX performance point + - description: MXC performance point required: - compatible @@ -72,8 +76,10 @@ examples: reg = <0x0aaf0000 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;