From patchwork Wed May 14 15:10:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 889949 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9E161DAC92; Wed, 14 May 2025 15:11:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747235491; cv=none; b=pX/FK4K9ZPN6rpJNUv6+2ciqbb+aX4iWMQ4+nFAOZGGsuCfRfQGA0ITzsKYMva61TldJjUm+SzCVkV97efU5XaDKqgqqTMzqmro5xcIlAWrkVST3Spa5c9bh7nog+o2h8It0yFnEoE7c1n3Hr2O3UpnmS18FZpM8DzpEXS8R9U4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747235491; c=relaxed/simple; bh=lYaGbx2VnhKo6X1FOzUp2xQ+2GU2i23LpGCoC5C4kvc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MbKgRFSQa0BrLxt0Lswcn4RyGPvk0D6VRfN/oBfbdzmSqlEv8GJv6qgEsTWCwp+hDnaLWf7bJd1LWZcDDglSz0+JNkeW+62umxwPtw8Pb7Hpl7Ugu4eYUg+Tdu06OVzDiPjc7OOLQaO+o1yfIhN/veyKzrnPaS//+7UbJkbCZZg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ElU4asIK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ElU4asIK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9C917C4CEED; Wed, 14 May 2025 15:11:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747235491; bh=lYaGbx2VnhKo6X1FOzUp2xQ+2GU2i23LpGCoC5C4kvc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ElU4asIK+UlcAY92/OP+e+k/onI8Yc6Sq/L67ku79gQjmLa4X1K4gZKOvkzLBaTv7 4QiToBm6pFxab/mIiIhVQeB2YCQWu80p69d6yVLX6BIItvUagj+4gEoYTbphTQJ/vq GdtHsocGnQZ+U6HDXzGnlKsd1ZEji3HZDTXrl0b6u6ZggLGyKOgOrswCy3ERNez3U5 TQbEvNfSar7m02/Ullv8ldZBovB6A/Xs+68VtucJ0tVXjRYwyJ2+7ogNlwonW9p0QM GSRC/qClehn/JlPSiU21iL/Vzj9ik/b0m1vyK/AK52r+CEjCDonV1TcqGXYh2tEn4w pd4luwIR3eEbw== From: Konrad Dybcio Date: Wed, 14 May 2025 17:10:29 +0200 Subject: [PATCH RFT v2 09/15] drm/msm/a6xx: Resolve the meaning of rgb565_predicator Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-topic-ubwc_central-v2-9-09ecbc0a05ce@oss.qualcomm.com> References: <20250514-topic-ubwc_central-v2-0-09ecbc0a05ce@oss.qualcomm.com> In-Reply-To: <20250514-topic-ubwc_central-v2-0-09ecbc0a05ce@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747235442; l=2420; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=KZjR/7FrP0LxsKBAjVMSyj1wk57rB6G7FY5USnkv3Fo=; b=uuZH1DYC8mMMmIZd3P98pZwOKmEq+5w0uwBHBF28oCPZEqw8iYi0YABLqV49qYIocPTWxhSgX SQPXosRN98SAd40muE3IkqEeACapM7lafLzES7dHAxugWQmGDixuXBS X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio It's supposed to be on when the UBWC encoder version is >= 4.0. Drop the per-GPU assignments. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 0a08837ab01b724489baeb217cc49779ddcdf146..5ee5f8dc90fe0d1647ce07b7dbcadc6ca2ecd416 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -592,7 +592,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (IS_ERR(gpu->common_ubwc_cfg)) return -EINVAL; - gpu->ubwc_config.rgb565_predicator = 0; gpu->ubwc_config.min_acc_len = 0; gpu->ubwc_config.ubwc_swizzle = 0x6; gpu->ubwc_config.macrotile_mode = 0; @@ -619,7 +618,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (adreno_is_a623(gpu)) { gpu->ubwc_config.highest_bank_bit = 16; - gpu->ubwc_config.rgb565_predicator = 1; gpu->ubwc_config.macrotile_mode = 1; } @@ -633,13 +631,11 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) adreno_is_a740_family(gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ gpu->ubwc_config.highest_bank_bit = 16; - gpu->ubwc_config.rgb565_predicator = 1; gpu->ubwc_config.macrotile_mode = 1; } if (adreno_is_a663(gpu)) { gpu->ubwc_config.highest_bank_bit = 13; - gpu->ubwc_config.rgb565_predicator = 1; gpu->ubwc_config.macrotile_mode = 1; gpu->ubwc_config.ubwc_swizzle = 0x4; } @@ -669,6 +665,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) */ BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13; + bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0; u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1)); bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg); bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0; @@ -677,7 +674,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, level2_swizzling_dis << 12 | - adreno_gpu->ubwc_config.rgb565_predicator << 11 | + rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | adreno_gpu->ubwc_config.min_acc_len << 3 | hbb_lo << 1 | ubwc_mode);