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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22fc8271aebsm104468735ad.107.2025.05.14.16.52.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 May 2025 16:52:45 -0700 (PDT) From: Jessica Zhang Date: Wed, 14 May 2025 16:52:32 -0700 Subject: [PATCH 4/5] drm/msm/dpu: Filter writeback modes using writeback maxlinewidth Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-max-mixer-width-v1-4-c8ba0d9bb858@oss.qualcomm.com> References: <20250514-max-mixer-width-v1-0-c8ba0d9bb858@oss.qualcomm.com> In-Reply-To: <20250514-max-mixer-width-v1-0-c8ba0d9bb858@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Abhinav Kumar Cc: Abhinav Kumar , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jessica Zhang X-Mailer: b4 0.15-dev-64971 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747266760; l=1350; i=jessica.zhang@oss.qualcomm.com; s=20230329; h=from:subject:message-id; bh=OIPNFYLkdGomhmus1/0s4dYazfcOvIpfe1g5WVjseBQ=; b=0lV/29bwfrvOOIXt1cQk9FuWEEWPvaC+02GdLvIzrV3TQ9b+8xL/6i24PUe+kv775VH6GIiyB PYZR7MOt/YnBvHbmvbU+ftLOqf6bUJy37F5YtG9ufV0E3xKiNFyxO3V X-Developer-Key: i=jessica.zhang@oss.qualcomm.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Proofpoint-GUID: oOTCRDybtrflGf0jpdFmApo5CD9zr7Ju X-Proofpoint-ORIG-GUID: oOTCRDybtrflGf0jpdFmApo5CD9zr7Ju X-Authority-Analysis: v=2.4 cv=JszxrN4C c=1 sm=1 tr=0 ts=68252ccf cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=IdaEjn1bWG-LatOizd0A:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDIyMiBTYWx0ZWRfXxsE0aMLtqMV7 cmAI+N4fUiU/hq9VIhjfZUgM8BMTKGWF1/fWgVoJkKx6a5C/ba5w5URW3dJ/p6Zf1zj/xxDZEVW slihTkEuNyHpEFobE3EEyxTya+oOtcl7BjzAFZP3+ZHdKZVJoTweh7tnHyo89cptMiHEN267h41 Ev8RTZkZ3/JxWJxsD2769kBcTVmSqLSegvwmxXRubv+6sX7aRqXZ8OM9Qx7lMdw/bodleE7K9M+ 6Vd8kIp2lhCjj9lpVc9IXsSrKCo4OtFV05n1mAViOf+izrzWVx3pQs8ZL856D/fwCQ1uLoCVNOf RMlep89M08hhPomiGrIIHhdb4BLgjG7oh5tiEK1x3boUomiptusBjofMQWyo3JykV/8rtye5uZ/ tae8rv5Ef/86eMiL2EtJFGmKaNdAu22vLsDpcin6QkEI2QuYvXa6JlX+pg72bMH7wfR/ITFP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_04,2025-05-14_03,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 bulkscore=0 malwarescore=0 mlxscore=0 adultscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505140222 Since the max mixer width is not a strict hardware limit, use the actual hardware limit (the writeback maxlinewidth) to filter modes. Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c index 8ff496082902..0a198896f656 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c @@ -14,14 +14,7 @@ static int dpu_wb_conn_get_modes(struct drm_connector *connector) struct msm_drm_private *priv = dev->dev_private; struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); - /* - * We should ideally be limiting the modes only to the maxlinewidth but - * on some chipsets this will allow even 4k modes to be added which will - * fail the per SSPP bandwidth checks. So, till we have dual-SSPP support - * and source split support added lets limit the modes based on max_mixer_width - * as 4K modes can then be supported. - */ - return drm_add_modes_noedid(connector, dpu_kms->catalog->caps->max_mixer_width, + return drm_add_modes_noedid(connector, dpu_kms->catalog->wb->maxlinewidth, dev->mode_config.max_height); }