From patchwork Thu May 8 16:19:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 888861 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4F5B280CD1; Thu, 8 May 2025 16:20:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746721208; cv=none; b=rKHGOzXyLFSGxB95K+LjvDvuZgPbiPT7+ajiCcDQC0Qu8mjzzlNaXvRkdII/2aV81fSK8fvnUUqRYuRhUkTDGWckdGN5MahFBKfFqQNaQbzNrCeogqgcEkkzMWNpfdN224YSy13EZ+HELpXwlus+Kledrhuoe9y0xBlVsHFK6sE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746721208; c=relaxed/simple; bh=/oA68eFBe5E8mmsg6F5TixcEt/kPA770I2QqKzPSfsI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=S3Y3vHDIyCWkNZhL6zzIF/wyQBIkLa6R7cCSXmYnd8rXZQ7tdgLOyHiYIPHf81BRo8GeLelQYzQDwp/WHtQpdAIVcXtQB9uxuR8ZmpsjONqKS7iKuXVW8HSixMqOo4Nhfv29XTCWoPZBFGbDKFkynFpboywDqPPUPc4LWAvS0rI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=GC0Q4R4U; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="GC0Q4R4U" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 548Dg1SV008709; Thu, 8 May 2025 16:19:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= c+YxeEgy/0njEoRBvcuzAAKLhzbxA4ZgdKXmQftvI6s=; b=GC0Q4R4UXegJElWb xp6mX43tNL9t/wi9qhBQuaq8l4gG1RRzPFeam1RXzLdJw08Ni3fc1c+1IOIuegHJ VFkgYRQAY/tZHMWMl/mR9Q86MzkBpsS9WAZPV4Okj3mR2r1YnEzFneY/95GZfwU2 PeFTIDHLtPUymH/+420u86MmRxBOySzLc4FonHzWs1ukoj5X1jW5TcukJKgCqgDV CV1XG1/cyswxOpQJOj0VxvvfekR7RD4s9tpCz48iDafCf9UWcsQiTa6SlxYfXEIb jt9mqYZ2qv0F2WRtZhCwoRVs2cyfPXaaLbVOGD6+twPJfZ31DYol7xjY5LuA1Hr0 ZRZasw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 46gnp59xks-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 May 2025 16:19:53 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 548GJqhq032560 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 8 May 2025 16:19:52 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 8 May 2025 09:19:46 -0700 From: Akhil P Oommen Date: Thu, 8 May 2025 21:49:20 +0530 Subject: [PATCH v3 2/3] arm64: dts: qcom: qcs8300: Add gpu and gmu nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250508-a623-gpu-support-v3-2-3cb31799d44e@quicinc.com> References: <20250508-a623-gpu-support-v3-0-3cb31799d44e@quicinc.com> In-Reply-To: <20250508-a623-gpu-support-v3-0-3cb31799d44e@quicinc.com> To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Dmitry Baryshkov CC: , , , , , Jie Zhang , "Akhil P Oommen" X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746721173; l=3418; i=quic_akhilpo@quicinc.com; s=20240726; h=from:subject:message-id; bh=U9LN1k/PoYST/y5hup9fuhUPNbh152ddfDme30oCAZs=; b=WO5SLA3ioYR1TwL+iIh0Jn68zPVSTiWqI603hWzIWWe7jT7erW/Jx+1my4sSizMHwKHTvW+nW dfrggqUn5DmCgNCc3tc3BvARx6ZaPkFpXCiFiQLIiCL+9TX2bkYX1ku X-Developer-Key: i=quic_akhilpo@quicinc.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=Lu2Symdc c=1 sm=1 tr=0 ts=681cd9a9 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=DOBxdMOjXtw3fjWlhrYA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: ik_QgGe1OFntlbErbes4Qj5pGmXahse1 X-Proofpoint-ORIG-GUID: ik_QgGe1OFntlbErbes4Qj5pGmXahse1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA4MDE0MiBTYWx0ZWRfXw9/WJoZTRzO/ ATOj5AmeKNmbnG/pcU1WlBC+D+xmeOmbSk5opElN69iR2wQ6yTwktg90N3jLND9mG56WYPs9xoh 9iBm4elyEUpdzUyoUVMeWNR+NPGFf7wmFBlDSK5+4MPYfOsGJt/DyY/gRuLJuCrTlHj1n1blMFJ +kpxn0z+wDUz8FXdHctp0hyZSotW2LoqYOgUXbolzT8Entl72vHBcSWrSAwSc42c42yCzw1MHzj xbTc/s5D3AN9NgsLbLgbyd3vetIWi4abqeII4+XHymzkU67IrwK8lZS3uJI/DKxbmyMIsk683S3 mWiL5Wi3RWUHjUEwaIxlxP3eihA+SQ/a4rsdrXwFDOiSwm67u2pSUuIO8eBjG9xgK/dqEY2VM2l UHK/JRX0Lwu/5eu/pGku+ykVqRda1cNgLBtCkhi3hlKeemg0+i52ixskYtCKGZz11MqvTmZG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-08_05,2025-05-08_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=791 priorityscore=1501 suspectscore=0 clxscore=1015 adultscore=0 malwarescore=0 spamscore=0 impostorscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505080142 From: Jie Zhang Add gpu and gmu nodes for qcs8300 chipset. Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 91 +++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 40771b062e8d7010dd93d7cc7b3db73cfa16bfdb..1dbccb9a0c75366aa6986b6adb4feb6164ee8845 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -2660,6 +2660,97 @@ serdes0: phy@8909000 { status = "disabled"; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-623.0", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + interrupts = ; + iommus = <&adreno_smmu 0 0xc00>, + <&adreno_smmu 1 0xc00>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + #cooling-cells = <2>; + + status = "disabled"; + + gpu_zap_shader: zap-shader { + memory-region = <&gpu_microcode_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-877000000 { + opp-hz = /bits/ 64 <877000000>; + opp-level = ; + opp-peak-kBps = <12484375>; + }; + + opp-780000000 { + opp-hz = /bits/ 64 <780000000>; + opp-level = ; + opp-peak-kBps = <10687500>; + }; + + opp-599000000 { + opp-hz = /bits/ 64 <599000000>; + opp-level = ; + opp-peak-kBps = <8171875>; + }; + + opp-479000000 { + opp-hz = /bits/ 64 <479000000>; + opp-level = ; + opp-peak-kBps = <5285156>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x34000>, + <0x0 0x03de0000 0x0 0x10000>, + <0x0 0x0b290000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub"; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", + "gx"; + iommus = <&adreno_smmu 5 0xc00>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,qcs8300-gpucc"; reg = <0x0 0x03d90000 0x0 0xa000>;