diff mbox series

[3/3] arm64: dts: qcom: sc8280xp: Add SLPI

Message ID 20250503-topic-8280_slpi-v1-3-9400a35574f7@oss.qualcomm.com
State New
Headers show
Series SC8280XP SLPI | expand

Commit Message

Konrad Dybcio May 2, 2025, 10:38 p.m. UTC 
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

SC8280XP features a SLPI (Sensor Low Power Island) core. Describe it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 72 ++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

Comments

Konrad Dybcio May 2, 2025, 10:57 p.m. UTC | #1 
On 5/3/25 12:55 AM, Dmitry Baryshkov wrote:
> On Sat, May 03, 2025 at 12:38:01AM +0200, Konrad Dybcio wrote:
>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> SC8280XP features a SLPI (Sensor Low Power Island) core. Describe it.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> Have your tried enabling it for X13s? Windows drivers provide
> qcslpi8280.mbn in the qcsubsys_ext_scss8280.cab cabinet.

Forgot to mention, it powers up and exposes the expected qrtr
service on the CRD

[...]

>> +			glink-edge {
>> +				interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
>> +							IPCC_MPROC_SIGNAL_GLINK_QMP
>> +							IRQ_TYPE_EDGE_RISING>;
>> +				mboxes = <&ipcc IPCC_CLIENT_SLPI
>> +						IPCC_MPROC_SIGNAL_GLINK_QMP>;
>> +
>> +				label = "slpi";
>> +				qcom,remote-pid = <3>;
> 
> No fastrpc contexts?

I frankly don't know how to validate them

Konrad
Dmitry Baryshkov May 3, 2025, 4:41 a.m. UTC | #2 
On Sat, May 03, 2025 at 12:57:26AM +0200, Konrad Dybcio wrote:
> On 5/3/25 12:55 AM, Dmitry Baryshkov wrote:
> > On Sat, May 03, 2025 at 12:38:01AM +0200, Konrad Dybcio wrote:
> >> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >>
> >> SC8280XP features a SLPI (Sensor Low Power Island) core. Describe it.
> >>
> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> > 
> > Have your tried enabling it for X13s? Windows drivers provide
> > qcslpi8280.mbn in the qcsubsys_ext_scss8280.cab cabinet.
> 
> Forgot to mention, it powers up and exposes the expected qrtr
> service on the CRD
> 
> [...]
> 
> >> +			glink-edge {
> >> +				interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
> >> +							IPCC_MPROC_SIGNAL_GLINK_QMP
> >> +							IRQ_TYPE_EDGE_RISING>;
> >> +				mboxes = <&ipcc IPCC_CLIENT_SLPI
> >> +						IPCC_MPROC_SIGNAL_GLINK_QMP>;
> >> +
> >> +				label = "slpi";
> >> +				qcom,remote-pid = <3>;
> > 
> > No fastrpc contexts?
> 
> I frankly don't know how to validate them

Well... The easiest way would be to upload fastrpc_shell_2 and attempt
to start sdsprpcd or hexagonrpcd.
Dmitry Baryshkov May 3, 2025, 5:52 a.m. UTC | #3 
On 03/05/2025 01:57, Konrad Dybcio wrote:
> On 5/3/25 12:55 AM, Dmitry Baryshkov wrote:
>> On Sat, May 03, 2025 at 12:38:01AM +0200, Konrad Dybcio wrote:
>>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>>
>>> SC8280XP features a SLPI (Sensor Low Power Island) core. Describe it.
>>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> Have your tried enabling it for X13s? Windows drivers provide
>> qcslpi8280.mbn in the qcsubsys_ext_scss8280.cab cabinet.
> 
> Forgot to mention, it powers up and exposes the expected qrtr
> service on the CRD

BTW: maybe you can include relevant DT parts for the CRD so that it 
doesn't stay unused?
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 3f9195da90ee898c68296f19dc55bcb3ac73fe29..75ec34bfa729946687c4c35aa9550685cac95a10 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -695,6 +695,11 @@  pil_adsp_mem: adsp-region@86c00000 {
 			no-map;
 		};
 
+		pil_slpi_mem: slpi-region@88c00000 {
+			reg = <0 0x88c00000 0 0x1500000>;
+			no-map;
+		};
+
 		pil_nsp0_mem: cdsp0-region@8a100000 {
 			reg = <0 0x8a100000 0 0x1e00000>;
 			no-map;
@@ -783,6 +788,30 @@  smp2p_nsp1_in: slave-kernel {
 		};
 	};
 
+	smp2p-slpi {
+		compatible = "qcom,smp2p";
+		qcom,smem = <481>, <430>;
+		interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc IPCC_CLIENT_SLPI
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <3>;
+
+		smp2p_slpi_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		smp2p_slpi_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
 	soc: soc@0 {
 		compatible = "simple-bus";
 		#address-cells = <2>;
@@ -2454,6 +2483,49 @@  tcsr: syscon@1fc0000 {
 			reg = <0x0 0x01fc0000 0x0 0x30000>;
 		};
 
+		remoteproc_slpi: remoteproc@2400000 {
+			compatible = "qcom,sc8280xp-slpi-pas", "qcom,sm8350-slpi-pas";
+			reg = <0 0x02400000 0 0x10000>;
+
+			interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd SC8280XP_LCX>,
+					<&rpmhpd SC8280XP_LMX>;
+			power-domain-names = "lcx", "lmx";
+
+			memory-region = <&pil_slpi_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_slpi_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
+							IPCC_MPROC_SIGNAL_GLINK_QMP
+							IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_SLPI
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "slpi";
+				qcom,remote-pid = <3>;
+			};
+		};
+
 		remoteproc_adsp: remoteproc@3000000 {
 			compatible = "qcom,sc8280xp-adsp-pas";
 			reg = <0 0x03000000 0 0x10000>;