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Wysocki" , Praveen Talari , , , , , CC: , , , , , , , Nikunj Kela Subject: [PATCH v3 3/9] dt-bindings: qcom: geni-se: describe SA8255p Date: Fri, 2 May 2025 08:40:12 +0530 Message-ID: <20250502031018.1292-4-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250502031018.1292-1-quic_ptalari@quicinc.com> References: <20250502031018.1292-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: NVhd4-dbQnFj7pXGAqjOIaNO-NXqHZ2i X-Proofpoint-ORIG-GUID: NVhd4-dbQnFj7pXGAqjOIaNO-NXqHZ2i X-Authority-Analysis: v=2.4 cv=UZZRSLSN c=1 sm=1 tr=0 ts=681437ce cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=gEfo2CItAAAA:8 a=COk6AnOGAAAA:8 a=v7CWcBsnNxNFVLN3aFYA:9 a=sptkURWiP4Gy88Gu7hUp:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAyMSBTYWx0ZWRfXxi0CxqslQwrp 53azCw6nLJ4AH1PIlo5oC2Jopb5HvcV+TMNazNXfnvAqPvXbWTr3MidWJcweowW+FSM/aCAKDOo 4gLQwsQIikYDNv59ffsbNY7HM2I0W/LBPw02d8jePPc1y46TLTBHUJASGFeyDNLdKZ03N+K9yL/ OERKRqcKWvg3aiAHbyQ9IHDZvQzIlPHPRRHWtVVH1hKHSVnGIMuOqLpACJQjWgNCKvwFCirigje cvXbJHU10YY3+nNloI17gHfoeKJVDwhn+hi1Z+Dr30ovGt+gh3PXM2AXzYSU5G842/BrFm3ys2L 1Bs6d60ce9Uol5tw2oTkh6ju7BpdeYU/iGFw+ru5MMwi/0jH3nyaTalLn5WPWW4IZFsNrrMNvPo 26uJ0L/+FzurOGxaSkRr1M1OLpWFQdqY2hKh6yoYBXlZWVk0uMYsdb6L+c6lzJLnfurHjj/Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 impostorscore=0 mlxscore=0 malwarescore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020021 From: Nikunj Kela SA8255p platform abstracts resources such as clocks, interconnect configuration in Firmware. Add DT bindings for the QUP Wrapper on sa8255p platform. Signed-off-by: Nikunj Kela Co-developed-by: Praveen Talari Signed-off-by: Praveen Talari v2 -> v3 - reordered required option v1 -> v2 - reorder sequence of tags in commit text - resolved waring errors while encountered in dt binding and dtb check. --- .../soc/qcom/qcom,sa8255p-geni-se-qup.yaml | 107 ++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml new file mode 100644 index 000000000000..b66c7c45a6ae --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,sa8255p-geni-se-qup.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GENI Serial Engine QUP Wrapper Controller + +maintainers: + - Praveen Talari + +description: + Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper + is a programmable module for supporting a wide range of serial interfaces + like UART, SPI, I2C, I3C, etc. A single QUP module can provide up to 8 Serial + Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP + Wrapper controller is modeled as a node with zero or more child nodes each + representing a serial engine. + +properties: + compatible: + const: qcom,sa8255p-geni-se-qup + + reg: + description: QUP wrapper common register address and length. + maxItems: 1 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + + iommus: + maxItems: 1 + + dma-coherent: true + +patternProperties: + "spi@[0-9a-f]+$": + type: object + description: GENI serial engine based SPI controller. SPI in master mode + supports up to 50MHz, up to four chip selects, programmable + data path from 4 bits to 32 bits and numerous protocol + variants. + additionalProperties: true + + properties: + compatible: + const: qcom,sa8255p-geni-spi + + "i2c@[0-9a-f]+$": + type: object + description: GENI serial engine based I2C controller. + additionalProperties: true + + properties: + compatible: + const: qcom,sa8255p-geni-i2c + + "serial@[0-9a-f]+$": + type: object + description: GENI Serial Engine based UART Controller. + additionalProperties: true + + properties: + compatible: + enum: + - qcom,sa8255p-geni-uart + - qcom,sa8255p-geni-debug-uart + +additionalProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + geniqup@9c0000 { + compatible = "qcom,sa8255p-geni-se-qup"; + reg = <0 0x9c0000 0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + serial@990000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0 0x990000 0 0x4000>; + interrupts = ; + power-domains = <&scmi0_pd 0>, <&scmi0_dvfs 0>; + power-domain-names = "power", "perf"; + }; + }; + }; +...