From patchwork Wed Apr 30 11:34:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 886115 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51F0F254859; Wed, 30 Apr 2025 11:35:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746012911; cv=none; b=IiNVRL5Sk8pCO4XzRIPvprWAy8cyf/FFJjF1zecLuUyb34mB11RLyb4Uj5vZyC5CjdLhJfa1iqrdjXFUa4oqH+a2Xgbd3j/xsVI5J6X3CVZQU3lCK8GRJZzfOP8MuG5/0ESGGwQBAvaurJnm1kkF7Na0OB2JIbaBbwGh1S6YpU4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746012911; c=relaxed/simple; bh=GwUKXnh+FVJsy+VeClv/2yX5qg5iEhQw/azoU36Eqoo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hIqJVacTb/ikJCB542Dhblg4PYq2z3QgM/jpKmqy5pm3xwNvXX8lKlWYvCxb5G2fgfR5VrygAogxlA5kRmbHxb4gwgc0aXiGTnwbAHSZZKysB1gnbmzHnk31jJCigp5UC0ESA4do3hTfSEVoTOFCtVRN/y3VsYTPjJGPIT1g1OA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uOC5hoDd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uOC5hoDd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CF30CC4CEEC; Wed, 30 Apr 2025 11:35:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746012911; bh=GwUKXnh+FVJsy+VeClv/2yX5qg5iEhQw/azoU36Eqoo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=uOC5hoDdv1oVbIrUlBwvXtLsNiQP1ThurUJnZMx16hFnXEtarn3vRcpJ0PcoRqwk8 eh98LgxlcGp++SDJAbfVMrNzuBnivlni8I1EF49ma+Dk2+Pilywj+qv8Ml/ekHzyqy 4/i67Mz4SAO2YclNxltUEYXW7S0/s5HxNlMr/5VP3XokpFmsiSnrYtt4OVY5x+g/f4 C6LXW39rb1Il8U+GUTHIjKTCCfaVRB4VeMC3nVDQXXPSAcnCshRyp7Nq1CkEozzfkU wOdJJ5XeEb8gmyiX46/FCxXf9oESN5SoLcUj49S2kIXRdqeqqNsQAlElLUY7z3smGJ YIuLk5HbndeUg== From: Konrad Dybcio Date: Wed, 30 Apr 2025 13:34:39 +0200 Subject: [PATCH RFT v6 5/5] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250430-topic-smem_speedbin_respin-v6-5-954ff66061cf@oss.qualcomm.com> References: <20250430-topic-smem_speedbin_respin-v6-0-954ff66061cf@oss.qualcomm.com> In-Reply-To: <20250430-topic-smem_speedbin_respin-v6-0-954ff66061cf@oss.qualcomm.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746012880; l=2805; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=V5Mdu0t8s6038X7jL5bKI4EfIFMP3ptl8Yd+DlwLKYE=; b=qQPJUvYTMPHisX1M2G+D+OwLnJrCPingfSYcdKAquSYG4Dk0Pxh4UMXz1M4HdBGf040+bv+JQ ioqGLG89BISDiC0IpLS48BEOQOLHyImC2YQYk4dNcQhxtkjRB63FJxh X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Add the speedbin masks to ensure only the desired OPPs are available on chips of a given bin. Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 82cabf777cd2c1dc87457aeede913873e7322ec2..1c006879bbfe01d7b20e6fab620affb61e31ecec 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2460,56 +2460,75 @@ zap-shader { memory-region = <&gpu_micro_code_mem>; }; - /* Speedbin needs more work on A740+, keep only lower freqs */ gpu_opp_table: opp-table { compatible = "operating-points-v2"; + opp-719000000 { + opp-hz = /bits/ 64 <719000000>; + opp-level = ; + opp-supported-hw = <0x1>; + }; + opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; opp-peak-kBps = <16500000>; + opp-supported-hw = <0x3>; }; opp-615000000 { opp-hz = /bits/ 64 <615000000>; opp-level = ; opp-peak-kBps = <12449218>; + opp-supported-hw = <0x3>; }; opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-level = ; opp-peak-kBps = <10687500>; + opp-supported-hw = <0x3>; }; opp-475000000 { opp-hz = /bits/ 64 <475000000>; opp-level = ; opp-peak-kBps = <6074218>; + opp-supported-hw = <0x3>; }; opp-401000000 { opp-hz = /bits/ 64 <401000000>; opp-level = ; opp-peak-kBps = <6074218>; + opp-supported-hw = <0x3>; }; opp-348000000 { opp-hz = /bits/ 64 <348000000>; opp-level = ; opp-peak-kBps = <6074218>; + opp-supported-hw = <0x3>; }; opp-295000000 { opp-hz = /bits/ 64 <295000000>; opp-level = ; opp-peak-kBps = <6074218>; + opp-supported-hw = <0x3>; }; opp-220000000 { opp-hz = /bits/ 64 <220000000>; opp-level = ; opp-peak-kBps = <2136718>; + opp-supported-hw = <0x3>; + }; + + opp-124800000 { + opp-hz = /bits/ 64 <124800000>; + opp-level = ; + opp-supported-hw = <0x3>; }; }; };