From patchwork Wed Apr 30 11:34:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 886519 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8F7D231829; Wed, 30 Apr 2025 11:34:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746012897; cv=none; b=a63E8R74Ls6yJCeZdRghqKmA1MK/VIE1F2gL1aZ+3FKXQzG7cmRmxPDq+2p+HxwRfa7uEMoFxJH3Fj1rEs2V+ldpP/cQam5J7DjcFyegj1aWAGdbQA+wGzMobx5loReIGnPD0ZoTeqvVRE0LZHaJm591GW4MQUfBVGSg+TFx+fk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746012897; c=relaxed/simple; bh=nvHCaF8qd9Kc8urkFp5so4scjDxpMQByuGnGWBLb67k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MgAPgS16ERnlsFzJMwIe+jOJT4vNBDmahwEjfJ4JSDjgPoTQhbytmU3TlOPa4z0ylxe1Ao1DRQem5+yLlzFp/NITVVuDlxP5vR7vEMZjpO9TBMmpPVS5nk0hBxqeQ5yvB6+B5MH1CFITBFIS30rv2zMq1nZkATBgLvk/IQHQ8EU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l2uojk/Q; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l2uojk/Q" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A987BC4CEE9; Wed, 30 Apr 2025 11:34:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746012896; bh=nvHCaF8qd9Kc8urkFp5so4scjDxpMQByuGnGWBLb67k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=l2uojk/Q7MsywuGQVGi82QAaos+ZqzmRniiGEdY0lUTIZ1DYWGiOlgO/ZhG6XPD1y WETk+G3QTw+NSC8kPH20jlxWQORBqk6Tj7awrCbevWXx1NZdBU3oUnu2KQMqRagty8 jHHC9bf66hGPvvZq6K7LuVMj0kAWrOkx6+O9a1IU+iFIxB4p4GkWus9SnRG7+G4VlT kmB8PZqicZGWW2U5TJyXifRH/kp7LkJSPpM3MKvoT/YnOCnQwnvwoV84FZ2ea6FP5r nKc09AQm/dbR4VJhDlW1AkHSkErpM9JhKzoCzDpjF9acKOxnGi6uUe5GuFUV6Dopyr SbJCqv4R/bUeA== From: Konrad Dybcio Date: Wed, 30 Apr 2025 13:34:36 +0200 Subject: [PATCH RFT v6 2/5] drm/msm/adreno: Add speedbin data for SM8550 / A740 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250430-topic-smem_speedbin_respin-v6-2-954ff66061cf@oss.qualcomm.com> References: <20250430-topic-smem_speedbin_respin-v6-0-954ff66061cf@oss.qualcomm.com> In-Reply-To: <20250430-topic-smem_speedbin_respin-v6-0-954ff66061cf@oss.qualcomm.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746012880; l=1547; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=s8amPV021nvmCFk5BsbFzQEAO5l0wK8PePLGYxCymEg=; b=M20YHKO9vKas3G0+FGjEatcTaoRgXamQ47q1mgVoAIrR1hBspD5dxyYSRUOY7LHw/IwqxcR1Q BEc6YmTSBfYDyTIpfQOZaoZ+Yh7h5YNXLdR3awkflU6Ix2++3c1mdih X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Add speebin data for A740, as found on SM8550 and derivative SoCs. For non-development SoCs it seems that "everything except FC_AC, FC_AF should be speedbin 1", but what the values are for said "everything" are not known, so that's an exercise left to the user.. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 53e2ff4406d8f0afe474aaafbf0e459ef8f4577d..61daa331567925e529deae5e25d6fb63a8ba8375 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -11,6 +11,9 @@ #include "a6xx.xml.h" #include "a6xx_gmu.xml.h" +#include +#include + static const struct adreno_reglist a612_hwcg[] = { {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, @@ -1431,6 +1434,11 @@ static const struct adreno_info a7xx_gpus[] = { }, .address_space_size = SZ_16G, .preempt_record_size = 4192 * SZ_1K, + .speedbins = ADRENO_SPEEDBINS( + { ADRENO_SKU_ID(SOCINFO_FC_AC), 0 }, + { ADRENO_SKU_ID(SOCINFO_FC_AF), 0 }, + /* Other feature codes (on prod SoCs) should match to speedbin 1 */ + ), }, { .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ .family = ADRENO_7XX_GEN2,