| Message ID | 20250430-b4-sm8750-display-v5-17-8cab30c3e4df@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | drm/msm: Add support for SM8750 | expand |
On Wed, Apr 30, 2025 at 03:00:47PM +0200, Krzysztof Kozlowski wrote: > Driver unconditionally saves current state on first init in > dsi_pll_7nm_init(), but does not save the VCO rate, only some of the > divider registers. The state is then restored during probe/enable via > msm_dsi_phy_enable() -> msm_dsi_phy_pll_restore_state() -> > dsi_7nm_pll_restore_state(). > > Restoring calls dsi_pll_7nm_vco_set_rate() with > pll_7nm->vco_current_rate=0, which basically overwrites existing rate of > VCO and messes with clock hierarchy, by setting frequency to 0 to clock > tree. This makes anyway little sense - VCO rate was not saved, so > should not be restored. > > If PLL was not configured configure it to minimum rate to avoid glitches > and configuring entire in clock hierarchy to 0 Hz. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > --- > > Changes in v5: > 1. New patch > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 6 ++++++ > 1 file changed, 6 insertions(+) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Please implement similar change into the 10nm driver. An alternative approach might be to do something like (14nm): cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 1a0f5c0509e6dcb04018c3e93aa704c7221a4869..9c7df9e00e027e8a8b1daad7c11dcfeeea52ca9d 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -861,6 +861,12 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) /* TODO: Remove this when we have proper display handover support */ msm_dsi_phy_pll_save_state(phy); + /* + * Store also proper vco_current_rate, because its value will be used in + * dsi_7nm_pll_restore_state(). + */ + if (!dsi_pll_7nm_vco_recalc_rate(&pll_7nm->clk_hw, VCO_REF_CLK_RATE)) + pll_7nm->vco_current_rate = pll_7nm->phy->cfg->min_pll_rate; return 0; }
Driver unconditionally saves current state on first init in dsi_pll_7nm_init(), but does not save the VCO rate, only some of the divider registers. The state is then restored during probe/enable via msm_dsi_phy_enable() -> msm_dsi_phy_pll_restore_state() -> dsi_7nm_pll_restore_state(). Restoring calls dsi_pll_7nm_vco_set_rate() with pll_7nm->vco_current_rate=0, which basically overwrites existing rate of VCO and messes with clock hierarchy, by setting frequency to 0 to clock tree. This makes anyway little sense - VCO rate was not saved, so should not be restored. If PLL was not configured configure it to minimum rate to avoid glitches and configuring entire in clock hierarchy to 0 Hz. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Changes in v5: 1. New patch --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 6 ++++++ 1 file changed, 6 insertions(+)