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[2a02:8388:6584:6400:d322:7350:96d2:429d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073e46501sm2147310f8f.73.2025.04.25.05.13.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 05:13:07 -0700 (PDT) From: Luca Weiss Subject: [PATCH 0/4] Add *_wait_val values for GDSCs in all SM6350 clock drivers Date: Fri, 25 Apr 2025 14:12:54 +0200 Message-Id: <20250425-sm6350-gdsc-val-v1-0-1f252d9c5e4e@fairphone.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAEZ8C2gC/x3MSwqAMAwA0atI1gZqNCpeRVwUjRrwRwNFEO9uc fkWMw+YBBWDLnsgSFTT80go8gzG1R+LoE7JQI7YVcRoe12yw2WyEaPf0Luipoap5WqGVF1BZr3 /Yz+87wfp1I/pYQAAAA== X-Change-ID: 20250425-sm6350-gdsc-val-a0162752854f To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , AngeloGioacchino Del Regno Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 As described in the commit messages, keep the GDSC configs aligned with the downstream kernel. For reference, this was checked using the following code: To: Bjorn Andersson To: Michael Turquette To: Stephen Boyd To: Konrad Dybcio To: AngeloGioacchino Del Regno Cc: ~postmarketos/upstreaming@lists.sr.ht Cc: phone-devel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Luca Weiss --- Luca Weiss (4): clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCs drivers/clk/qcom/camcc-sm6350.c | 18 ++++++++++++++++++ drivers/clk/qcom/dispcc-sm6350.c | 3 +++ drivers/clk/qcom/gcc-sm6350.c | 6 ++++++ drivers/clk/qcom/gpucc-sm6350.c | 6 ++++++ 4 files changed, 33 insertions(+) --- base-commit: 9c32cda43eb78f78c73aee4aa344b777714e259b change-id: 20250425-sm6350-gdsc-val-a0162752854f Best regards, diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index fa5fe4c2a2ee..049fcbefba50 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -402,7 +402,7 @@ static bool gdsc_get_hwmode(struct generic_pm_domain *domain, struct device *dev static int gdsc_init(struct gdsc *sc) { - u32 mask, val; + u32 mask, val, tmp; int on, ret; /* @@ -420,6 +420,14 @@ static int gdsc_init(struct gdsc *sc) if (!sc->clk_dis_wait_val) sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL; + regmap_read(sc->regmap, sc->gdscr, &tmp); + if (sc->en_rest_wait_val != ((tmp >> EN_REST_WAIT_SHIFT) & 0xf)) + printk(KERN_ERR "gdsc_init: %s en_rest_wait_val mismatch: (new) 0x%x vs 0x%x (reset)\n", sc->pd.name, sc->en_rest_wait_val, (tmp >> EN_REST_WAIT_SHIFT) & 0xf); + if (sc->en_few_wait_val != ((tmp >> EN_FEW_WAIT_SHIFT) & 0xf)) + printk(KERN_ERR "gdsc_init: %s en_few_wait_val mismatch: (new) 0x%x vs 0x%x (reset)\n", sc->pd.name, sc->en_few_wait_val, (tmp >> EN_FEW_WAIT_SHIFT) & 0xf); + if (sc->clk_dis_wait_val != ((tmp >> CLK_DIS_WAIT_SHIFT) & 0xf)) + printk(KERN_ERR "gdsc_init: %s clk_dis_wait_val mismatch: (new) 0x%x vs 0x%x (reset)\n", sc->pd.name, sc->clk_dis_wait_val, (tmp >> CLK_DIS_WAIT_SHIFT) & 0xf); + val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT | sc->en_few_wait_val << EN_FEW_WAIT_SHIFT | sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT;