From patchwork Fri Apr 25 12:00:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 884586 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F56823F296; Fri, 25 Apr 2025 12:00:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745582408; cv=none; b=HkTq4a4PkEd5MTQEipHua0b1SRCXTwnFU3SjXZCIo5iNGpZDPRMk+UX1EFOGf+KIYtMNcdRSSS+UtZj7t3k5P/0oWIqC7IRfN2+2TneQl3BJn4QYlVCYLoepJsL9QeGr+mtdp3UWAn9j102ikUtF5LVRQSNZHBVPocb9EXN12jQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745582408; c=relaxed/simple; bh=y7mtw6+FUzq5sQIQsg0DALHPrQWOm0H73hleZx5lEtA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SYSwZb3O9eUCdCi1BzBDJRi9DkCLAUnJ3oXoyhLgi7bLVI0H6+6fdzJP5NGXA4wLVvKH67M+ggXmlgwV6yKYnMLtRydV8slWgRWtyj+cN5cyiWrWJ01XvdwexlZ6TZUEEwYY7tkqnc4BxF8MdSXJCiZzSTod+kcUpbJwY5eT6wU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cit6gzLF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cit6gzLF" Received: by smtp.kernel.org (Postfix) with ESMTPS id F2120C4CEED; Fri, 25 Apr 2025 12:00:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745582408; bh=y7mtw6+FUzq5sQIQsg0DALHPrQWOm0H73hleZx5lEtA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=cit6gzLF460YQXJJIdBWql3i2/Us904co5tn7yMMQ2L13gOQ8t6WnqdvyIoReE4VB k9UtJPSLSpiznGgMxQtf9NNUR5Fr0+b6dsr/2/MzanCvkShv4FWIyoTuqJnfjsE9+n c5sREWhZ4aR2U6ix2vj1MkqraeWErRW8j76duMG2p3sEcnUINCYlr38QdB/Tl/U/VC hqI8NLKNOQsVnwBcQRMZmzPNJJJ7RBNUdl5kgmtVP3AM6EgOcFYY+P45N/OhdksGgn VH8n5TlyeQrSVx76tLQ+7BX4ldGpJvF9kGXSEy+POt2BF9aK/AbxuxyMLN1VEFt4Il /JHbDd2GFCH0w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDC3FC369C2; Fri, 25 Apr 2025 12:00:07 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 25 Apr 2025 16:00:02 +0400 Subject: [PATCH v8 1/2] arm64: dts: qcom: ipq5018: Add PCIe related nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250425-ipq5018-pcie-v8-1-03ee75c776dc@outlook.com> References: <20250425-ipq5018-pcie-v8-0-03ee75c776dc@outlook.com> In-Reply-To: <20250425-ipq5018-pcie-v8-0-03ee75c776dc@outlook.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nitheesh Sekar , Varadarajan Narayanan , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Bjorn Andersson , Konrad Dybcio , Praveenkumar I Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, George Moussalem , 20250317100029.881286-1-quic_varada@quicinc.com, 20250317100029.881286-2-quic_varada@quicinc.com, Sricharan R , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1745582405; l=7947; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=TBPQ5Gx5v7GQ746HC2P0zzVYqSzT/5a7T7FVqwq5EqI=; b=ZbRlpfRcm6jR7CIHjDV5WBwt5C8xgLy8FhfePdyhrgOX46KK5fovmPaLOjuII/QOgwP3K6Rlx Xwb28Lz4ybBCudZgTXeDI5/FEMwddyiGCKComNH93i7HEEJj1EtX0dd X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Nitheesh Sekar Add phy and controller nodes for a 2-lane Gen2 and a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and one global interrupt. NOTE: the PCIe controller supports gen3, yet the phy is limited to gen2. Signed-off-by: Nitheesh Sekar Signed-off-by: Sricharan R Reviewed-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 246 +++++++++++++++++++++++++++++++++- 1 file changed, 244 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 8914f2ef0bc47fda243b19174f77ce73fc10757d..917c6eb7c227e405e9216125cff15551f57839a5 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -147,6 +147,40 @@ usbphy0: phy@5b000 { status = "disabled"; }; + pcie1_phy: phy@7e000{ + compatible = "qcom,ipq5018-uniphy-pcie-phy"; + reg = <0x0007e000 0x800>; + + clocks = <&gcc GCC_PCIE1_PIPE_CLK>; + + resets = <&gcc GCC_PCIE1_PHY_BCR>, + <&gcc GCC_PCIE1PHY_PHY_BCR>; + + #clock-cells = <0>; + #phy-cells = <0>; + + num-lanes = <1>; + + status = "disabled"; + }; + + pcie0_phy: phy@86000{ + compatible = "qcom,ipq5018-uniphy-pcie-phy"; + reg = <0x00086000 0x1000>; + + clocks = <&gcc GCC_PCIE0_PIPE_CLK>; + + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + + #clock-cells = <0>; + #phy-cells = <0>; + + num-lanes = <2>; + + status = "disabled"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5018-tlmm"; reg = <0x01000000 0x300000>; @@ -170,8 +204,8 @@ gcc: clock-controller@1800000 { reg = <0x01800000 0x80000>; clocks = <&xo_board_clk>, <&sleep_clk>, - <0>, - <0>, + <&pcie0_phy>, + <&pcie1_phy>, <0>, <0>, <0>, @@ -387,6 +421,214 @@ frame@b128000 { status = "disabled"; }; }; + + pcie1: pcie@80000000 { + compatible = "qcom,pcie-ipq5018"; + reg = <0x80000000 0xf1d>, + <0x80000f20 0xa8>, + <0x80001000 0x1000>, + <0x00078000 0x3000>, + <0x80100000 0x1000>, + <0x0007b000 0x1000>; + reg-names = "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + /* + * While the PCIe controller supports gen3, + * the phy is limited to gen2. Hence, limit + * the link speed to gen2. + */ + max-link-speed = <2>; + + phys = <&pcie1_phy>; + phy-names ="pciephy"; + + ranges = <0x01000000 0 0x00000000 0x80200000 0 0x00100000>, + <0x02000000 0 0x80300000 0x80300000 0 0x10000000>; + + msi-map = <0x0 &v2m0 0x0 0xff8>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 142 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 143 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 144 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 145 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, + <&gcc GCC_PCIE1_AXI_M_CLK>, + <&gcc GCC_PCIE1_AXI_S_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_AUX_CLK>, + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>; + clock-names = "iface", + "axi_m", + "axi_s", + "ahb", + "aux", + "axi_bridge"; + + resets = <&gcc GCC_PCIE1_PIPE_ARES>, + <&gcc GCC_PCIE1_SLEEP_ARES>, + <&gcc GCC_PCIE1_CORE_STICKY_ARES>, + <&gcc GCC_PCIE1_AXI_MASTER_ARES>, + <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE1_AHB_ARES>, + <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>; + reset-names = "pipe", + "sleep", + "sticky", + "axi_m", + "axi_s", + "ahb", + "axi_m_sticky", + "axi_s_sticky"; + + status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie0: pcie@a0000000 { + compatible = "qcom,pcie-ipq5018"; + reg = <0xa0000000 0xf1d>, + <0xa0000f20 0xa8>, + <0xa0001000 0x1000>, + <0x00080000 0x3000>, + <0xa0100000 0x1000>, + <0x00083000 0x1000>; + reg-names = "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + + /* + * While the PCIe controller supports gen3, + * the phy is limited to gen2. Hence, limit + * the link speed to gen2. + */ + max-link-speed = <2>; + + phys = <&pcie0_phy>; + phy-names ="pciephy"; + + ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>, + <0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>; + + msi-map = <0x0 &v2m0 0x0 0xff8>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, + <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>; + clock-names = "iface", + "axi_m", + "axi_s", + "ahb", + "aux", + "axi_bridge"; + + resets = <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_SLEEP_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; + reset-names = "pipe", + "sleep", + "sticky", + "axi_m", + "axi_s", + "ahb", + "axi_m_sticky", + "axi_s_sticky"; + + status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; }; timer {