| Message ID | 20250423072044.234024-6-loic.poulain@oss.qualcomm.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v4,1/6] media: qcom: camss: Add support for TFE (Spectra 340) | expand |
Hi Krzysztof, Bryan On Thu, Apr 24, 2025 at 5:51 PM Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On 24/04/2025 09:53, Loic Poulain wrote: > > Hi Krzysztof, > > > > On Thu, Apr 24, 2025 at 9:37 AM Krzysztof Kozlowski <krzk@kernel.org> wrote: > >> > >> On Wed, Apr 23, 2025 at 09:20:43AM GMT, Loic Poulain wrote: > >>> + power-domains: > >>> + items: > >>> + - description: GDSC CAMSS Block, Global Distributed Switch Controller. > >>> + > >>> + vdda-csiphy-1p2-supply: > >>> + description: > >>> + Phandle to a 1.2V regulator supply to CSI PHYs. > >>> + > >>> + vdda-pll-1p8-supply: > >> > >> > >> How are the pins or input supplies called? > > > > Pins are called: > > - VDD_A_CSI_0_1P2 (for csiphy 0) > > - VDD_A_CSI_1_1P2 (for csiphy 1) > > OK. This however starts new questions: why aren't there separate nodes > for the CSI PHY controllers? These are separate blocks with their own > address space, own power rails, own interrupts and own clocks. > > > (both of the above are supplied together without individual control) > > - VDD_A_CAMSS_PLL_1P8 > This does not need voltage name then. I've been trying to follow the various threads on this topic, but it seems there's no consensus yet. So wouldn't it be more practical to use the regular/simple bindings, similar to those used for the SM8250? - vdda-phy-supply - vdda-pll-supply I understand that more complex bindings, including voltage, CSIPHY index, etc., are not necessary here, + this will likely be replaced by the long-term effort to establish dedicated nodes for the CSIPHYs. Regards, Loic
On 29/04/2025 14:08, Loic Poulain wrote: >> OK. This however starts new questions: why aren't there separate nodes >> for the CSI PHY controllers? These are separate blocks with their own >> address space, own power rails, own interrupts and own clocks. >> >>> (both of the above are supplied together without individual control) >>> - VDD_A_CAMSS_PLL_1P8 >> This does not need voltage name then. > I've been trying to follow the various threads on this topic, but it > seems there's no consensus yet. So wouldn't it be more practical > to use the regular/simple bindings, similar to those used for the SM8250? > - vdda-phy-supply > - vdda-pll-supply > > I understand that more complex bindings, including voltage, CSIPHY > index, etc., are not necessary here, + this will likely be replaced The thing is we know that a single rail for all phys is not correct. The choices are 1. Continue on as before 2. Do something interim re: my proposal on csiphy#-XpY-supply @ 0.9, 1.2 and/or 1.8 per PHY 3. Move to defined PHY nodes like just about every other PHY in qcom let alone linux -> dsi, usb, ethernet Its pretty clear from the DT people which way we should go. So, I've already started working on making individual PHY nodes based on our recent conversations. I think tbh that we should push merging new SoCs and just solve this problem outright. We can aim to merge the remainder of x1e, as well as all of qcm2290 and sm8650 for 6.17 then with the new PHY structure. --- bod
On 4/29/25 16:18, Bryan O'Donoghue wrote: > On 29/04/2025 14:08, Loic Poulain wrote: >>> OK. This however starts new questions: why aren't there separate nodes >>> for the CSI PHY controllers? These are separate blocks with their own >>> address space, own power rails, own interrupts and own clocks. >>> >>>> (both of the above are supplied together without individual control) >>>> - VDD_A_CAMSS_PLL_1P8 >>> This does not need voltage name then. >> I've been trying to follow the various threads on this topic, but it >> seems there's no consensus yet. So wouldn't it be more practical >> to use the regular/simple bindings, similar to those used for the SM8250? >> - vdda-phy-supply >> - vdda-pll-supply >> >> I understand that more complex bindings, including voltage, CSIPHY >> index, etc., are not necessary here, + this will likely be replaced > > The thing is we know that a single rail for all phys is not correct. > > The choices are > > 1. Continue on as before > 2. Do something interim re: my proposal on > csiphy#-XpY-supply @ 0.9, 1.2 and/or 1.8 per PHY > 3. Move to defined PHY nodes like just about every other PHY in qcom let > alone linux -> dsi, usb, ethernet > > Its pretty clear from the DT people which way we should go. > > So, I've already started working on making individual PHY nodes based on > our recent conversations. > > I think tbh that we should push merging new SoCs and just solve this > problem outright. > > We can aim to merge the remainder of x1e, as well as all of qcm2290 and > sm8650 for 6.17 then with the new PHY structure. > If so, add SM8650 to the pile. -- Best wishes, Vladimir
diff --git a/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml new file mode 100644 index 000000000000..fa870872f80b --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml @@ -0,0 +1,243 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,qcm2290-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCM2290 Camera Subsystem (CAMSS) + +maintainers: + - Loic Poulain <loic.poulain@oss.qualcomm.com> + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,qcm2290-camss + + reg: + maxItems: 9 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csiphy0 + - const: csiphy1 + - const: csitpg0 + - const: csitpg1 + - const: top + - const: vfe0 + - const: vfe1 + + clocks: + maxItems: 15 + + clock-names: + items: + - const: ahb + - const: axi + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + - const: csi0 + - const: csi1 + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: top_ahb + - const: vfe0 + - const: vfe0_cphy_rx + - const: vfe1 + - const: vfe1_cphy_rx + + interrupts: + maxItems: 8 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csiphy0 + - const: csiphy1 + - const: csitpg0 + - const: csitpg1 + - const: vfe0 + - const: vfe1 + + interconnects: + maxItems: 3 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + - const: sf_mnoc + + iommus: + maxItems: 4 + + power-domains: + items: + - description: GDSC CAMSS Block, Global Distributed Switch Controller. + + vdda-csiphy-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSI PHYs. + + vdda-pll-1p8-supply: + description: + Phandle to 1.8V regulator supply to CAMSS refclk pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-3]+$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + description: + Input port for receiving CSI data from a CSIPHY. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - vdda-csiphy-1p2-supply + - vdda-pll-1p8-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-qcm2290.h> + #include <dt-bindings/interconnect/qcom,rpm-icc.h> + #include <dt-bindings/interconnect/qcom,qcm2290.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camss: camss@5c6e000 { + compatible = "qcom,qcm2290-camss"; + + reg = <0x0 0x5c6e000 0x0 0x1000>, + <0x0 0x5c75000 0x0 0x1000>, + <0x0 0x5c52000 0x0 0x1000>, + <0x0 0x5c53000 0x0 0x1000>, + <0x0 0x5c66000 0x0 0x400>, + <0x0 0x5c68000 0x0 0x400>, + <0x0 0x5c11000 0x0 0x1000>, + <0x0 0x5c6f000 0x0 0x4000>, + <0x0 0x5c76000 0x0 0x4000>; + reg-names = "csid0", + "csid1", + "csiphy0", + "csiphy1", + "csitpg0", + "csitpg1", + "top", + "vfe0", + "vfe1"; + + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMSS_AXI_CLK>, + <&gcc GCC_CAMSS_NRT_AXI_CLK>, + <&gcc GCC_CAMSS_RT_AXI_CLK>, + <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, + <&gcc GCC_CAMSS_CPHY_0_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CPHY_1_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_TFE_0_CLK>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_1_CLK>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>; + clock-names = "ahb", + "axi", + "camnoc_nrt_axi", + "camnoc_rt_axi", + "csi0", + "csi1", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "top_ahb", + "vfe0", + "vfe0_cphy_rx", + "vfe1", + "vfe1_cphy_rx"; + + interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csid0", + "csid1", + "csiphy0", + "csiphy1", + "csitpg0", + "csitpg1", + "vfe0", + "vfe1"; + + interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG + &config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>, + <&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, + <&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc"; + + iommus = <&apps_smmu 0x400 0x0>, + <&apps_smmu 0x800 0x0>, + <&apps_smmu 0x820 0x0>, + <&apps_smmu 0x840 0x0>; + + power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; + + vdda-csiphy-1p2-supply = <&pm4125_l5>; + vdda-pll-1p8-supply = <&pm4125_l13>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + };
Add bindings for qcom,qcm2290-camss in order to support the camera subsystem found in the Qualcomm Robotics RB1 Platform (QRB2210). Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> --- .../bindings/media/qcom,qcm2290-camss.yaml | 243 ++++++++++++++++++ 1 file changed, 243 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml