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([84.226.118.249]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d82a041d4sm182244665e9.0.2025.03.31.14.57.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Mar 2025 14:57:25 -0700 (PDT) From: Aleksandrs Vinarskis To: Bjorn Andersson , Krzysztof Kozlowski , Dmitry Baryshkov , Aleksandrs Vinarskis , Konrad Dybcio , Greg Kroah-Hartman , Abel Vesa , Johan Hovold , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heikki Krogerus Subject: [PATCH v1 1/6] arm64: dts: qcom: move pcie6a type change from X1P42100 to X1P42100-crd Date: Mon, 31 Mar 2025 23:53:35 +0200 Message-ID: <20250331215720.19692-2-alex.vinarskis@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250331215720.19692-1-alex.vinarskis@gmail.com> References: <20250331215720.19692-1-alex.vinarskis@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 It appears at least on some devices (Asus Zenbook A14, x1-26-100) change of pcie6a_phy's compatible breaks the controller. Move compatible change from generic x1p42100.dtsi to CRD's specific x1p42100-crd.dts instead. Signed-off-by: Aleksandrs Vinarskis --- arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 ++++ arch/arm64/boot/dts/qcom/x1p42100.dtsi | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts index cf07860a63e9..a2a212b31556 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts @@ -15,3 +15,7 @@ / { model = "Qualcomm Technologies, Inc. X1P42100 CRD"; compatible = "qcom,x1p42100-crd", "qcom,x1p42100"; }; + +&pcie6a_phy { + compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi index 27f479010bc3..4424a8708d39 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi @@ -37,10 +37,6 @@ &pcie3 { num-lanes = <4>; }; -&pcie6a_phy { - compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy"; -}; - &soc { /* The PCIe3 PHY on X1P42100 uses a different IP block */ pcie3_phy: phy@1bd4000 {