From patchwork Wed Mar 26 08:10:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 876346 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B1401A0BCD; Wed, 26 Mar 2025 08:11:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742976664; cv=none; b=Cj6Qxp/SqI8mDRQz10q5gZ0NY9j/3CebmVgDv0lVZGX9sgHD+ANR/2uOOP3SeJ1FAS7YqYRq3Gy1WOG+7Zfqo2kdnnoGqU/iB/JRLO0MYBahDCYeLURb00qRQQ0SONstJR6qOViig6oWVtiJUngqugPww1t+nE7vO7GUKJ4yCZk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742976664; c=relaxed/simple; bh=gR/j5qAdGCDtCQy0dd8RZSzdFIIk90FGMUJmnZcVeoc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OTAAObSjec6Psiqlm/Tj7jREd595xoZ2zaMcPdiCiMUW0Dm5sP6btVcUNDHzOLFyxPHHc/AOrfXXvMW3eBN9qYV0w5Ah4a06/6haFtHWbhIdoqYUZzaz1qinawchcfS67eygn3VbHm63eO2VGM2RthhHQE0kgEmEgRJKK07oXbM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mMXRYIwa; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mMXRYIwa" Received: by smtp.kernel.org (Postfix) with ESMTPS id C3E96C4CEF2; Wed, 26 Mar 2025 08:11:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742976663; bh=gR/j5qAdGCDtCQy0dd8RZSzdFIIk90FGMUJmnZcVeoc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=mMXRYIwasdyRC/A0kqvlETTzRaNd5IDpvg4yxB6VqHJCpW1HMF6oDxXT1+d/x1rz9 wGBSrC5XVs580rPD7IF1Szk9F/GwnLf/P3sitT3aY+y1LrCMhR026nth6rzqmKAH+n SwarAfIB6XFDNJtYoBsD6ZzxT8Wwj2pReatcdI/YdGQsREnqpD9Vv5HwL7K2shyEJk CCt40Q7s9r9niaxNxM/nqr9/fJ0kq5qaop60O4RfIw/A/w2K46DEhai40gyjFroT7n cL8ooj49A2H5+ybMmJEMe7/vhqapdtI7UvFP700PQTQyIpvArnv1qmeI6aaGRzRyp0 Ka8uQphHr8Haw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC9C4C36011; Wed, 26 Mar 2025 08:11:03 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 26 Mar 2025 12:10:56 +0400 Subject: [PATCH v7 2/6] phy: qualcomm: qcom-uniphy-pcie 28LP add support for IPQ5018 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250326-ipq5018-pcie-v7-2-e1828fef06c9@outlook.com> References: <20250326-ipq5018-pcie-v7-0-e1828fef06c9@outlook.com> In-Reply-To: <20250326-ipq5018-pcie-v7-0-e1828fef06c9@outlook.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nitheesh Sekar , Varadarajan Narayanan , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Bjorn Andersson , Konrad Dybcio , Praveenkumar I Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, George Moussalem , 20250317100029.881286-1-quic_varada@quicinc.com, 20250317100029.881286-2-quic_varada@quicinc.com, Sricharan Ramabadhran , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1742976660; l=2535; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=kYH6vXN/WlVTNUTrZPgBDmJJfb+EoAkdo/0WziGGijo=; b=Ma/+ghqQ1vbu85eRfMhm40tdOdvQ/+8Gmo/1EOCdGV6tE0sBXPzZjL17x7NHV+9e7JNQrsgmc IovVQfcOn6iAfGAOk7O8jjYSFXn5Dms/U43reXLfSvivjtgABeJ/mZj X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Nitheesh Sekar The Qualcomm UNIPHY PCIe PHY 28LP is found on both IPQ5332 and IPQ5018. Adding the PHY init sequence, pipe clock rate, and compatible for IPQ5018. Signed-off-by: Nitheesh Sekar Signed-off-by: Sricharan Ramabadhran Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem --- drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 45 ++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c index c8b2a3818880ea3bf7bee67f5c1c075c1ac650e4..324c0a5d658e43e03597b285e761d3604761508e 100644 --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c @@ -75,6 +75,40 @@ struct qcom_uniphy_pcie { #define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy) +static const struct qcom_uniphy_pcie_regs ipq5018_regs[] = { + { + .offset = SSCG_CTRL_REG_4, + .val = 0x1cb9, + }, { + .offset = SSCG_CTRL_REG_5, + .val = 0x023a, + }, { + .offset = SSCG_CTRL_REG_3, + .val = 0xd360, + }, { + .offset = SSCG_CTRL_REG_1, + .val = 0x1, + }, { + .offset = SSCG_CTRL_REG_2, + .val = 0xeb, + }, { + .offset = CDR_CTRL_REG_4, + .val = 0x3f9, + }, { + .offset = CDR_CTRL_REG_5, + .val = 0x1c9, + }, { + .offset = CDR_CTRL_REG_2, + .val = 0x419, + }, { + .offset = CDR_CTRL_REG_1, + .val = 0x200, + }, { + .offset = PCS_INTERNAL_CONTROL_2, + .val = 0xf101, + }, +}; + static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = { { .offset = PHY_CFG_PLLCFG, @@ -88,6 +122,14 @@ static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = { }, }; +static const struct qcom_uniphy_pcie_data ipq5018_data = { + .lane_offset = 0x800, + .phy_type = PHY_TYPE_PCIE_GEN2, + .init_seq = ipq5018_regs, + .init_seq_num = ARRAY_SIZE(ipq5018_regs), + .pipe_clk_rate = 125 * MEGA, +}; + static const struct qcom_uniphy_pcie_data ipq5332_data = { .lane_offset = 0x800, .phy_type = PHY_TYPE_PCIE_GEN3, @@ -212,6 +254,9 @@ static inline int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, int id) static const struct of_device_id qcom_uniphy_pcie_id_table[] = { { + .compatible = "qcom,ipq5018-uniphy-pcie-phy", + .data = &ipq5018_data, + }, { .compatible = "qcom,ipq5332-uniphy-pcie-phy", .data = &ipq5332_data, }, {