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Tue, 25 Mar 2025 05:30:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEjMUj1TLOsrYDkG5M5EtFQfcFnxQW3340OpNyCVSxp8cds6pRnYowPm6jrN3KQxqvr/9ZaFg== X-Received: by 2002:a05:6a00:c92:b0:736:3c77:31fd with SMTP id d2e1a72fcca58-73905a364b0mr22153500b3a.23.1742905842630; Tue, 25 Mar 2025 05:30:42 -0700 (PDT) Received: from hu-prashk-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7390618e4b6sm9987391b3a.180.2025.03.25.05.30.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Mar 2025 05:30:42 -0700 (PDT) From: Prashanth K To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: cros-qcom-dts-watchers@chromium.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pratham Pratap , Prashanth K Subject: [PATCH v1 5/5] arm64: dts: qcom: qdu1000: Add snps,dis_u3_susphy_quirk Date: Tue, 25 Mar 2025 18:00:19 +0530 Message-Id: <20250325123019.597976-6-prashanth.k@oss.qualcomm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250325123019.597976-1-prashanth.k@oss.qualcomm.com> References: <20250325123019.597976-1-prashanth.k@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: xWHwCcauh4FovA_QETDtsk0Ppl87DFtx X-Proofpoint-ORIG-GUID: xWHwCcauh4FovA_QETDtsk0Ppl87DFtx X-Authority-Analysis: v=2.4 cv=CPoqXQrD c=1 sm=1 tr=0 ts=67e2a1f4 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=1HEuz3GWIXJSLhVaKDMA:9 a=uG9DUKGECoFWVXl0Dc02:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-25_05,2025-03-25_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=893 spamscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 phishscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503250088 From: Pratham Pratap During device mode initialization on certain QC targets, before the runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI} register write fails. As a result, GEVTADDR registers are still 0x0. Upon setting runstop bit, DWC3 controller attempts to write the new events to address 0x0, causing an SMMU fault and system crash. This was initially observed on SM8450 and later reported on few other targets as well. As suggested by Qualcomm HW team, clearing the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register write failures. Address this by setting the snps,dis_u3_susphy_quirk to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year and hasn't exhibited any side effects. Signed-off-by: Pratham Pratap Signed-off-by: Prashanth K --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index f973aa8f7477..b3c673e24726 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1022,6 +1022,7 @@ usb_1_dwc3: usb@a600000 { iommus = <&apps_smmu 0xc0 0x0>; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk;