| Message ID | 20250321-qcom_ipq5424_cmnpll-v1-1-3ea8e5262da4@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add CMN PLL clock controller support for IPQ5424 | expand |
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml index f869b3739be8..bbaf896ae908 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml @@ -25,6 +25,7 @@ properties: compatible: enum: - qcom,ipq9574-cmn-pll + - qcom,ipq5424-cmn-pll reg: maxItems: 1 diff --git a/include/dt-bindings/clock/qcom,ipq-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h index 936e92b3b62c..e30d57001c38 100644 --- a/include/dt-bindings/clock/qcom,ipq-cmn-pll.h +++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H @@ -19,4 +19,12 @@ #define ETH1_50MHZ_CLK 7 #define ETH2_50MHZ_CLK 8 #define ETH_25MHZ_CLK 9 + +/* + * The CMN PLL output clock rates that are specifically applicable for IPQ5424 + * SoC. For IPQ5424, the other output clocks and their rates are same as IPQ9574. + */ +#define NSS_300MHZ_CLK 4 +#define PPE_375MHZ_CLK 5 + #endif
The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference input clock. The output clocks are the same as IPQ9574 SoC, except for the clock rate of output clocks to PPE and NSS. Also, add macros for clock rates that are applicable specifically only for IPQ5424. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> --- .../devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 + include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 10 +++++++++- 2 files changed, 10 insertions(+), 1 deletion(-)