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Thu, 20 Mar 2025 05:55:10 +0000 Received: from APTAIPPMTA01.qualcomm.com (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 52K5t8tc014233; Thu, 20 Mar 2025 05:55:10 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 52K5t9BY014360 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 20 Mar 2025 05:55:10 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 4635958) id DAC8740BF4; Thu, 20 Mar 2025 13:55:08 +0800 (CST) From: Wenbin Yao To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, quic_qianyu@quicinc.com, sfr@canb.auug.org.au, linux-arm-kernel@lists.infradead.org Cc: quic_wenbyao@quicinc.com Subject: [PATCH v1 2/3] arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3 Date: Thu, 20 Mar 2025 13:55:01 +0800 Message-Id: <20250320055502.274849-3-quic_wenbyao@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250320055502.274849-1-quic_wenbyao@quicinc.com> References: <20250320055502.274849-1-quic_wenbyao@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: jAJmnuebdXgPMRuQ7AEFghltwy0xoHkP X-Authority-Analysis: v=2.4 cv=INICChvG c=1 sm=1 tr=0 ts=67dbadc0 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=R2ixBC5xtkv2JAc71vkA:9 a=sagSQ8oKcmm4XqVqbL8I:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: jAJmnuebdXgPMRuQ7AEFghltwy0xoHkP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-20_01,2025-03-19_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 clxscore=1015 mlxlogscore=945 impostorscore=0 phishscore=0 mlxscore=0 spamscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503200035 From: Qiang Yu Add pcie3port node to represent the PCIe bridge of PCIe3 so that PCI slot voltage rails can be described under this node in the board's dts. Signed-off-by: Qiang Yu Signed-off-by: Wenbin Yao --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 46b79fce9..32e8d400a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3287,6 +3287,16 @@ opp-128000000 { opp-peak-kBps = <15753000 1>; }; }; + pcie3port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3_phy: phy@1be0000 {