From patchwork Thu Mar 13 11:03:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 873203 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F5CF266B46; Thu, 13 Mar 2025 11:04:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741863899; cv=none; b=Olmd8zA4DQzjn3x9Av7GvGciaB2npfOLN7Ocj6r78lTF2h+bXdptrij28DpbapMCcu69S9qMLYk9D/1cY27E8BP9xU2mE6lB27w6RhNWazSzF4lzJfIg24VaLUzD3FJHp4idotO5GuLIdT4Tkv3Ctbfcd8Hdq1nttNCCY+0yktE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741863899; c=relaxed/simple; bh=yWtrbpvYp75wlG1QEFxQ3/8RimR+H13dRoertSitiXE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LX5BMjS++u6A4ZzAgf+lLlpT6tG4TH77BBk7O5UoUEFniVmbfsQZfKXcn2KN7+TThpyMZBxmVVRmFMHvx4gAYlmSDzVOgtX0eWCsOGxsIaIHMzLiHsdY7yEvZ7t6nfcj81jLYpdC8EIn1wC4W00q7Xb3mDBGf0Lq4UslqFCnfK8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=SMAYlTvO; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="SMAYlTvO" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 52D9ESLB015151; Thu, 13 Mar 2025 11:04:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= /k/9aYDZpXmXBBZLTYAzx6u+M8qE5P0QFwVaLmPz6Vc=; b=SMAYlTvOXlZSXuQr Txz+1YQl5goeePosKbDXBJLSCrEUw/3kNybEdol6bcqiqG80qtABpw0UvyHx9p1w svg6w2D/C5bpwnRlCSZ3i79hN9a4OWqzpUKxAGdA9EZQjwDEBU+NDX1AfBvMb0xE Lfc32Y/fc9KJT0DTcf9Jmef/tUiYGBTivH9TrmmByRY3OnjSo+E+9UCss/Aksl7e JjN39/S+A0XPco0qsbpSH9u4+PboQ+ahNxczxGcED7C163pcFQycWB9DtA/0pKHt L7/s4y+uonA5lc+LOR6BN9YhjfbTv1LcE261HwmjLkEMoT2uDB/Ml8MwuZGQ9+Wi ePoe9Q== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45au2nwkpm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Mar 2025 11:04:35 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52DB4Yxd012956 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Mar 2025 11:04:34 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 13 Mar 2025 04:04:25 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v12 2/6] clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock Date: Thu, 13 Mar 2025 16:33:55 +0530 Message-ID: <20250313110359.242491-3-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250313110359.242491-1-quic_mmanikan@quicinc.com> References: <20250313110359.242491-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: kBLnP1zOMxaZM6dnQTsf7tNMCLU-OPDH X-Authority-Analysis: v=2.4 cv=ZObXmW7b c=1 sm=1 tr=0 ts=67d2bbc3 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=pA53Pz_bmLzdSEi0sq0A:9 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: kBLnP1zOMxaZM6dnQTsf7tNMCLU-OPDH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-13_05,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 mlxscore=0 suspectscore=0 adultscore=0 impostorscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 clxscore=1011 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503130087 From: Devi Priya Add support for gpll0_out_aux clock which acts as the parent for certain networking subsystem (nss) clocks. Reviewed-by: Dmitry Baryshkov Signed-off-by: Devi Priya Signed-off-by: Manikanta Mylavarapu --- Changes in V12: - No change. drivers/clk/qcom/gcc-ipq9574.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 6bb66a7e1fb6..6dc86e686de4 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -108,6 +108,20 @@ static struct clk_alpha_pll_postdiv gpll0 = { }, }; +static struct clk_alpha_pll_postdiv gpll0_out_aux = { + .offset = 0x20000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpll0_out_aux", + .parent_hws = (const struct clk_hw *[]) { + &gpll0_main.clkr.hw + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + static struct clk_alpha_pll gpll4_main = { .offset = 0x22000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], @@ -3896,6 +3910,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, + [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr, }; static const struct qcom_reset_map gcc_ipq9574_resets[] = {