| Message ID | 20250125035920.2651972-3-quic_mmanikan@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add PCIe support for IPQ5424 | expand |
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml index 1230183fc0a9..fac7922d2473 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml @@ -35,8 +35,6 @@ properties: - description: PCIE 2-lane PHY3 pipe clock source '#power-domain-cells': false - '#interconnect-cells': - const: 1 required: - compatible @@ -54,6 +52,9 @@ allOf: clocks: maxItems: 5 + '#interconnect-cells': + const: 1 + - if: properties: compatible: @@ -65,6 +66,9 @@ allOf: minItems: 7 maxItems: 7 + '#interconnect-cells': + const: 2 + unevaluatedProperties: false examples:
Interconnect cells differ between the IPQ5332 and IPQ5424. Therefore, update the interconnect cells according to the SoC. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> --- .../devicetree/bindings/clock/qcom,ipq5332-gcc.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)