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Fri, 10 Jan 2025 07:21:25 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2e92794sm88714725e9.37.2025.01.10.07.21.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jan 2025 07:21:25 -0800 (PST) From: Neil Armstrong Date: Fri, 10 Jan 2025 16:21:19 +0100 Subject: [PATCH 2/4] arm64: dts: qcom: sm8650: add OSM L3 node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250110-topic-sm8650-ddr-bw-scaling-v1-2-041d836b084c@linaro.org> References: <20250110-topic-sm8650-ddr-bw-scaling-v1-0-041d836b084c@linaro.org> In-Reply-To: <20250110-topic-sm8650-ddr-bw-scaling-v1-0-041d836b084c@linaro.org> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add the OSC L3 Cache controller node. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 86684cb9a9325618ddb74458621cf4bbdc1cc0d1..bc09e879c1440873a52daf3fc7a38f451f1f972c 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5506,6 +5506,16 @@ rpmhpd_opp_turbo_l1: opp-416 { }; }; + epss_l3: interconnect@17d90000 { + compatible = "qcom,sm8650-epss-l3", "qcom,epss-l3"; + reg = <0 0x17d90000 0 0x1000>; + + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@17d91000 { compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x17d91000 0 0x1000>,