From patchwork Sat Dec 7 16:15:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 848117 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52D6D1917D9; Sat, 7 Dec 2024 16:18:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733588283; cv=none; b=c/98M6Y8yrl2qckKpjXN7Xy4Lw3cQ1CgUQJAcBSJeUt501iPYXpOwhXzAd5yrYh5oQhuLCKZEY0BUq7m0K/WixtPTIpJEk+DMaCw3BWPHuA3GXVSjmWPrp2DXJvd8LaWWpYF3c1AiEwq97+WAtOZOufJLJSRlUrsT1GJjJxQiZ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733588283; c=relaxed/simple; bh=tGcTGZBdk808F/NK25zh1z1OPF8aAj3ycpvYHyPriAQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Rt+1EVR4lwXJGo/lSzXHvoJ23CW27H2I27zuSq1ZJgYi6j/I0mm+SA9NJlkIgk6wPa8g4NSUzBxjrC+ET6lE7qQYQN8tLA2MeZulbetRttRLTF2xwcxy+EkGJFpi/R5A8/fGOSOGBOcbAzp7QClelfmA39rNiygtg8Fm0khWvZI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=YkghaRza; arc=none smtp.client-ip=209.85.210.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YkghaRza" Received: by mail-pf1-f169.google.com with SMTP id d2e1a72fcca58-725aa5c597cso2331669b3a.1; Sat, 07 Dec 2024 08:18:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1733588281; x=1734193081; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Egv1uLLtlIR3aubbAbZDOIXdcxKbfhpt7HeuljF3hFc=; b=YkghaRzaOoTZr+nbNC1llc6w4pRtidnC2l1FSJWwZ1GfURWh7MpXp9/Ks471WECQqU cXPccKFfR2PLdbRY0E2BMntfc8vIG2p5uoeKEF1nSJl9Z0fYTw5AMFk7uNEYFlGve2Ja TpuxOseGBqG7r4+vmbDnyT7AC1ScAztTyqVpAEXMzN7PuGRQgv3NsdP2PVevJsYkJACj aUgDzLHMuIWJ7h3WRNw4faVADgulskakc5XaZN2vGYuzkvUwY1pJcaX9YlmlujmOJgqx L9blRoeN6Z/BFKlac29ZvTLfjq3AHGKo9Dx7UpHXVi1Nt9yD+2BdKSDy5xfwcCEoahxX wr5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733588281; x=1734193081; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Egv1uLLtlIR3aubbAbZDOIXdcxKbfhpt7HeuljF3hFc=; b=Z1aeJEBOczl+M013wx95z75K08pAsR2F5P0BAkQ9ibQfWTBkdK2halR7q6pNLdVDmh ltQT6xbqETaaRx2+z+8sKDP8nAsEIKJLx7jpvc0qivfHsBXaiDLY33JN1vHF1qFed6vc ebCbrs9LukSw3NJtML6et32kMYGlKak76IBSTq3iHbGcXRpKcdZys9iuNGANs4MFhQ26 eMouIpUI5rsOyNxCDq/d7CvfgsR2zdzuFu62wXRSJxAxi8iaZT3z3DuSoCD9HSUebqCn AePLa0rTecyJ9OB4kEDQsuM5a7p/7pS3n2jFlx1FRXBl4KdLfuFb0UOLIHzvqeldaLuq Gg1Q== X-Forwarded-Encrypted: i=1; AJvYcCUwlxiXb78KtoKBvqvEDzW3i/NtMFlGQmeSXXnfBOe15WULkn9zt8bWQxb6V/m9PDbWs5ELyzU1MQUzqVO6@vger.kernel.org, AJvYcCXTD6ILhd+H4bjuncxCCTEe0LyEb9BTCOjCc9lWEkTyDeuf/bDnOCg2gFsrfvwkT6n8yBo3CIX0GqLTyNUS@vger.kernel.org X-Gm-Message-State: AOJu0YyxuO0jGj/ed3hDuBZGUwbIBJsK23tMkOhhijh8ZyKcO1RAx0PH 2nnSwflLqDzMYIXOHw/d9flwsFTVSwA0VdzqfdBdnCu3yzSj21u/ X-Gm-Gg: ASbGncvQNZfsTvx5fkx7B2XSGZyBzEOefQleCugVAaky0jkMCZU1bgyyAdm+ogSSOaA p0OWfev8uTRiRo1xJu33va19OhsR69+/T1d4WH/l8LNmAC7X7lpZ5bib5th0ntsl3ypBNHI329W xq6xqWT0h99ELl0UepB0zoLzA+aH0d7kipefwnZfEcNSNKbr6mK1+M+GlvxMmq63bWEjPpw413i a/zyd9ReftU9GqQFqxyE/jTjaOnbPQ+78KD7pFWA/ucyfAUjMZNJTGCgdrBCJbNXJPxyFS818st 9ADv1L/y X-Google-Smtp-Source: AGHT+IHhk4V5sRBXUwQ9Yocv9BWmM2RNwIxei2ATn5zpP5G7+85uR/g8Hd5cxybxh40GaRhyv+IIIw== X-Received: by 2002:a17:902:f651:b0:216:30f9:93d4 with SMTP id d9443c01a7336-21630f995b5mr29663105ad.8.1733588280606; Sat, 07 Dec 2024 08:18:00 -0800 (PST) Received: from localhost (c-73-37-105-206.hsd1.or.comcast.net. [73.37.105.206]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7fd156e14afsm4168293a12.30.2024.12.07.08.17.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Dec 2024 08:17:59 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Connor Abbott , Akhil P Oommen , Rob Clark , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [RFC 13/24] drm/msm: Lazily create context VM Date: Sat, 7 Dec 2024 08:15:13 -0800 Message-ID: <20241207161651.410556-14-robdclark@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241207161651.410556-1-robdclark@gmail.com> References: <20241207161651.410556-1-robdclark@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Rob Clark In the next commit, a way for userspace to opt-in to userspace managed VM is added. For this to work, we need to defer creation of the VM until it is needed. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 ++- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 ++++++----- drivers/gpu/drm/msm/msm_drv.c | 29 ++++++++++++++++++++----- drivers/gpu/drm/msm/msm_gem_submit.c | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 9 +++++++- 5 files changed, 42 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 79a692288d18..97ec1dedeb98 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -112,6 +112,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, { bool sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; struct msm_context *ctx = submit->queue->ctx; + struct drm_gpuvm *vm = msm_context_vm(submit->dev, ctx); struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; phys_addr_t ttbr; u32 asid; @@ -120,7 +121,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, if (ctx->seqno == ring->cur_ctx_seqno) return; - if (msm_iommu_pagetable_params(to_msm_vm(ctx->vm)->mmu, &ttbr, &asid)) + if (msm_iommu_pagetable_params(to_msm_vm(vm)->mmu, &ttbr, &asid)) return; if (adreno_gpu->info->family >= ADRENO_7XX_GEN1) { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 3104ad878cf1..033c1c9c457e 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -313,6 +313,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx, { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct drm_device *drm = gpu->dev; + struct drm_gpuvm *vm = msm_context_vm(drm, ctx); /* No pointer params yet */ if (*len != 0) @@ -358,8 +359,8 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx, *value = 0; return 0; case MSM_PARAM_FAULTS: - if (ctx->vm) - *value = gpu->global_faults + to_msm_vm(ctx->vm)->faults; + if (vm) + *value = gpu->global_faults + to_msm_vm(vm)->faults; else *value = gpu->global_faults; return 0; @@ -367,14 +368,14 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx, *value = gpu->suspend_count; return 0; case MSM_PARAM_VA_START: - if (ctx->vm == gpu->vm) + if (vm == gpu->vm) return UERR(EINVAL, drm, "requires per-process pgtables"); - *value = ctx->vm->mm_start; + *value = vm->mm_start; return 0; case MSM_PARAM_VA_SIZE: - if (ctx->vm == gpu->vm) + if (vm == gpu->vm) return UERR(EINVAL, drm, "requires per-process pgtables"); - *value = ctx->vm->mm_range; + *value = vm->mm_range; return 0; case MSM_PARAM_HIGHEST_BANK_BIT: *value = adreno_gpu->ubwc_config.highest_bank_bit; diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index ab0998c2e846..7a23549db97d 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -214,10 +214,29 @@ static void load_gpu(struct drm_device *dev) mutex_unlock(&init_lock); } +/** + * msm_context_vm - lazily create the context's VM + * + * @dev: the drm device + * @ctx: the context + * + * The VM is lazily created, so that userspace has a chance to opt-in to having + * a userspace managed VM before the VM is created. + * + * Note that this does not return a reference to the VM. Once the VM is created, + * it exists for the lifetime of the context. + */ +struct drm_gpuvm *msm_context_vm(struct drm_device *dev, struct msm_context *ctx) +{ + struct msm_drm_private *priv = dev->dev_private; + if (!ctx->vm) + ctx->vm = msm_gpu_create_private_vm(priv->gpu, current); + return ctx->vm; +} + static int context_init(struct drm_device *dev, struct drm_file *file) { static atomic_t ident = ATOMIC_INIT(0); - struct msm_drm_private *priv = dev->dev_private; struct msm_context *ctx; ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); @@ -230,7 +249,6 @@ static int context_init(struct drm_device *dev, struct drm_file *file) kref_init(&ctx->ref); msm_submitqueue_init(dev, ctx); - ctx->vm = msm_gpu_create_private_vm(priv->gpu, current); file->driver_priv = ctx; ctx->seqno = atomic_inc_return(&ident); @@ -408,7 +426,7 @@ static int msm_ioctl_gem_info_iova(struct drm_device *dev, * Don't pin the memory here - just get an address so that userspace can * be productive */ - return msm_gem_get_iova(obj, ctx->vm, iova); + return msm_gem_get_iova(obj, msm_context_vm(dev, ctx), iova); } static int msm_ioctl_gem_info_set_iova(struct drm_device *dev, @@ -417,18 +435,19 @@ static int msm_ioctl_gem_info_set_iova(struct drm_device *dev, { struct msm_drm_private *priv = dev->dev_private; struct msm_context *ctx = file->driver_priv; + struct drm_gpuvm *vm = msm_context_vm(dev, ctx); if (!priv->gpu) return -EINVAL; /* Only supported if per-process address space is supported: */ - if (priv->gpu->vm == ctx->vm) + if (priv->gpu->vm == vm) return UERR(EOPNOTSUPP, dev, "requires per-process pgtables"); if (should_fail(&fail_gem_iova, obj->size)) return -ENOMEM; - return msm_gem_set_iova(obj, ctx->vm, iova); + return msm_gem_set_iova(obj, vm, iova); } static int msm_ioctl_gem_info_set_metadata(struct drm_gem_object *obj, diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c index 51c92fe1146f..5e37e1dad5bb 100644 --- a/drivers/gpu/drm/msm/msm_gem_submit.c +++ b/drivers/gpu/drm/msm/msm_gem_submit.c @@ -63,7 +63,7 @@ static struct msm_gem_submit *submit_create(struct drm_device *dev, kref_init(&submit->ref); submit->dev = dev; - submit->vm = queue->ctx->vm; + submit->vm = msm_context_vm(dev, queue->ctx); submit->gpu = gpu; submit->cmd = (void *)&submit->bos[nr_bos]; submit->queue = queue; diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index ad6f14891205..5efbca0b9fb1 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -354,7 +354,12 @@ struct msm_context { */ int queueid; - /** @vm: the per-process GPU address-space */ + /** + * @vm: + * + * The per-process GPU address-space. Do not access directly, use + * msm_context_vm(). + */ struct drm_gpuvm *vm; /** @kref: the reference count */ @@ -439,6 +444,8 @@ struct msm_context { atomic64_t ctx_mem; }; +struct drm_gpuvm *msm_context_vm(struct drm_device *dev, struct msm_context *ctx); + /** * msm_gpu_convert_priority - Map userspace priority to ring # and sched priority *