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Wed, 27 Nov 2024 09:32:39 GMT Received: from congzhan2-gv.ap.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 27 Nov 2024 01:32:33 -0800 From: Cong Zhang Date: Wed, 27 Nov 2024 17:32:20 +0800 Subject: [PATCH] arm64: dts: qcom: Correct IRQ number of EL2 non-secure physical timer Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241127-correct_timer_irq-v1-1-ce4309b655bd@quicinc.com> X-B4-Tracking: v=1; b=H4sIACTnRmcC/33PwWrDMAwG4FcJOk/DVtx0KWPsPUYJnqqsgiZZZ C9slLz73PSy0y6CX6BP0hWSmEqCQ3UFk0WTTmMJ/qECPsfxQ1BPJQM5Ct5TgzyZCecu6yDWqc3 o61pcLGXfEpS5T5Nevzfz7XjPJvNXofO9CYOkFDf6UD3fZNfSDmdOT7VznY6aNV66U06KC6HD0 AYOro8UA70WiXXkR56GF7j5Z015sp/thcVvC/65dvHosfE7x3t67xuu/4JwXNf1FzrYG+YUAQA A X-Change-ID: 20241126-correct_timer_irq-133e0a33e792 To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , Cong Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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In linux, the IRQ number has a fixed 16 offset for PPIs. Therefore, the linux IRQ number of EL2 non-secure physical timer should be 10 (26 - 16). Signed-off-by: Cong Zhang --- The EL2 non-secure physical timer is utilized during kernel bootup in EL2 mode with KVM enabled. This patch has been verified on the QCS8300 platform with KVM enabled. Given that the dependency patch has already been reviewed, I am uncertain whether it is preferable to submit this fix as a new patch or to combine it with the dependency patch. I would appreciate your suggestions on this patch. --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) --- base-commit: 6ad9d5070ae9de51803b16ffc384c23d62466c7d change-id: 20241126-correct_timer_irq-133e0a33e792 prerequisite-message-id: <20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com> prerequisite-patch-id: 73c78f31fa1d504124d4a82b578a6a14126cccd8 prerequisite-patch-id: 5a01283c8654ae7c696d9c69cb21505b71c5ca27 prerequisite-patch-id: dc633d5aaac790776a8a213ea2faa4890a3f665d prerequisite-patch-id: 9ecf4cb8b5842ac64e51d6baa0e6c1fbe449ee66 Best regards, diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 2c35f96c3f289d5e2e57e0e30ef5e17cd1286188..de6c368efb3a5efeaf628babdb7e91f8cbbf9d5f 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -1370,6 +1370,6 @@ arch_timer: timer { interrupts = , , , - ; + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 5f7e59ecf1ca6298cb252ee0654bc7eaeefbd303..b0775173278f3eed0f301b40dfba0f2680d7b0d0 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -1548,6 +1548,6 @@ timer { interrupts = , , , - ; + ; }; };