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Miller" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: , , , , , Konrad Dybcio Subject: [PATCH V2 2/2] arm64: dts: qcom: qcs8300: enable the inline crypto engine Date: Fri, 22 Nov 2024 18:50:44 +0530 Message-ID: <20241122132044.30024-3-quic_yrangana@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241122132044.30024-1-quic_yrangana@quicinc.com> References: <20241122132044.30024-1-quic_yrangana@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: SesfVmFuL0qbzlpUvKnS8PEA9biqWBfU X-Proofpoint-GUID: SesfVmFuL0qbzlpUvKnS8PEA9biqWBfU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 mlxlogscore=901 suspectscore=0 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411220112 Add an ICE node to qcs8300 SoC description and enable it by adding a phandle to the UFS node. Reviewed-by: Konrad Dybcio Signed-off-by: Yuvaraj Ranganathan --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 2c35f96c3f28..ab91c3b7bba6 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -685,6 +685,7 @@ &mc_virt SLAVE_EBI1 0>, <0 0>, <0 0>, <0 0>; + qcom,ice = <&ice>; status = "disabled"; }; @@ -710,6 +711,13 @@ ufs_mem_phy: phy@1d87000 { status = "disabled"; }; + ice: crypto@1d88000 { + compatible = "qcom,qcs8300-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x01d88000 0x0 0x18000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>;