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Thu, 7 Nov 2024 09:50:54 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 7 Nov 2024 01:50:49 -0800 From: Luo Jie Date: Thu, 7 Nov 2024 17:50:25 +0800 Subject: [PATCH v6 4/5] arm64: dts: qcom: Add CMN PLL node for IPQ9574 SoC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241107-qcom_ipq_cmnpll-v6-4-a5cfe09de485@quicinc.com> References: <20241107-qcom_ipq_cmnpll-v6-0-a5cfe09de485@quicinc.com> In-Reply-To: <20241107-qcom_ipq_cmnpll-v6-0-a5cfe09de485@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730973028; l=3971; i=quic_luoj@quicinc.com; s=20240808; h=from:subject:message-id; bh=/WDvojlj2mcpFyiCGayq35c6ymsFrEnUVMEInolKWrI=; b=cpYeAkAtQ402QESW3PvyPbMBtjd2HZI6G4ZgGYdsEtJeUMT/3kK9p7bv70FTgPct6Tgo+kO7X ToCMHhinJXPA9DTNvGbnJ6sAMlvocHmx7IhOUpE+5TjRwnU37BCPN7j X-Developer-Key: i=quic_luoj@quicinc.com; a=ed25519; pk=P81jeEL23FcOkZtXZXeDDiPwIwgAHVZFASJV12w3U6w= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: A1pzE9L8Hnvuk9XpipgPYOlQYGsZHI6s X-Proofpoint-ORIG-GUID: A1pzE9L8Hnvuk9XpipgPYOlQYGsZHI6s X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 bulkscore=0 adultscore=0 malwarescore=0 phishscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411070074 The CMN PLL clock controller allows selection of an input clock rate from a defined set of input clock rates. It in-turn supplies fixed rate output clocks to the hardware blocks that provide the ethernet functions such as PPE (Packet Process Engine) and connected switch or PHY, and to GCC. The reference clock of CMN PLL is routed from XO to the CMN PLL through the internal WiFi block. .XO (48 MHZ or 96 MHZ)-->WiFi (multiplier/divider)-->48 MHZ to CMN PLL. The reference input clock from WiFi to CMN PLL is fully controlled by the bootstrap pins which select the XO frequency (48 MHZ or 96 MHZ). Based on this frequency, the divider in the internal Wi-Fi block is automatically configured by hardware (1 for 48 MHZ, 2 for 96 MHZ), to ensure output clock to CMN PLL is 48 MHZ. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 16 ++++++++++++++- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 26 +++++++++++++++++++++++- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi index 91e104b0f865..78f6a2e053d5 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -3,7 +3,7 @@ * IPQ9574 RDP board common device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -164,6 +164,20 @@ &usb3 { status = "okay"; }; +/* + * The bootstrap pins for the board select the XO clock frequency, + * which automatically enables the right dividers to ensure the + * reference clock output from WiFi is 48 MHZ. + */ +&ref_48mhz_clk { + clock-div = <1>; + clock-mult = <1>; +}; + &xo_board_clk { clock-frequency = <24000000>; }; + +&xo_clk { + clock-frequency = <48000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 14c7b3a78442..8246a00a3e3e 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -3,10 +3,11 @@ * IPQ9574 SoC device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include +#include #include #include #include @@ -19,6 +20,12 @@ / { #size-cells = <2>; clocks { + ref_48mhz_clk: ref-48mhz-clk { + compatible = "fixed-factor-clock"; + clocks = <&xo_clk>; + #clock-cells = <0>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -28,6 +35,11 @@ xo_board_clk: xo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; + + xo_clk: xo-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; }; cpus { @@ -243,6 +255,18 @@ mdio: mdio@90000 { status = "disabled"; }; + cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq9574-cmn-pll"; + reg = <0x0009b000 0x800>; + clocks = <&ref_48mhz_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names = "ref", "ahb", "sys"; + #clock-cells = <1>; + assigned-clocks = <&cmn_pll CMN_PLL_CLK>; + assigned-clock-rates-u64 = /bits/ 64 <12000000000>; + }; + qfprom: efuse@a4000 { compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; reg = <0x000a4000 0x5a1>;