From patchwork Fri Oct 4 08:03:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 833062 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C624713D520; Fri, 4 Oct 2024 08:05:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728029102; cv=none; b=KV6+UO668Lfk32bwoSAHkqCJA50SD9oNAuSFw24NQEyj26M46ibZUg/+iK3Q4RL9lxE8jHJP4XrLUqRd6pgQl6n0qLqy9+wuILbxuz0PlA015+N7lE4JQuQwIG+2LFJqdcES4fbinuSCWckh8/8TdVopr4vXKxGqDI+i/kcJbd8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728029102; c=relaxed/simple; bh=P7BLLubReR6/io0Q7+j88spivn/C6qz1cWzsUOn2yxo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=snclYj0n/MZl/Sg95X1An7jHt71kh5zQzCPLZIAjCrR0I0F1mfsr96Xw+LVBy2xfUYsIukR60luz/tbZpMQSZyZycWuacVk4hmhBnCffNSb4nZBI5P4yKg3CnETRfqsaeKPiKtNtxWAMGBaISfVGvb2UD5W1e1ZqpXyFo4VdY3I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=jar30oR+; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="jar30oR+" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 493HxmW2011606; Fri, 4 Oct 2024 08:04:44 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= TrRzMxwqkU6Azk83y6Byhm1KcxZwoS/LonOuwGLvIy8=; b=jar30oR+XRGg/WQb W0f6pw0KqKLbGW9BoNeyt8beSxh6QmzmmJnrB92y4DRwjjd0l0khikbSE/t4EjQg x2X3siIBn73WxyZpHeFLhLYxAbTR2AOgMjFEjOEJJfShwNs4rgX2MFkuauffbbqf A8w8Rg9Qwc9mTz6WNZ/RAhAf4Fm/3DidDiL2x7uAJ5ytRM48cfEnVzo1eNmnvNJl GY/ATxh0qhTMrqBYecBl5EC+f6Z4TeZ3cKPOEo73RLUEUf/ZovoXbi1pMbPXeXp9 YMReyqawfdzOAh9muge+6Yb94Tbca0wubZwfv2q0OUyEpThUWZ2LFHhOqNvIjRnC Ype1Aw== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42205k9e3v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 04 Oct 2024 08:04:43 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49484g8I022598 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 4 Oct 2024 08:04:43 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 4 Oct 2024 01:04:35 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v6 6/7] arm64: dts: qcom: ipq9574: Add nsscc node Date: Fri, 4 Oct 2024 13:33:31 +0530 Message-ID: <20241004080332.853503-7-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241004080332.853503-1-quic_mmanikan@quicinc.com> References: <20241004080332.853503-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: SeU8G78kDA_cC0-KpFaHrBiPxZd_BXwh X-Proofpoint-ORIG-GUID: SeU8G78kDA_cC0-KpFaHrBiPxZd_BXwh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 clxscore=1015 impostorscore=0 mlxlogscore=989 malwarescore=0 spamscore=0 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040057 From: Devi Priya Add a node for the nss clock controller found on ipq9574 based devices. Signed-off-by: Devi Priya Signed-off-by: Manikanta Mylavarapu --- Changes in V6: - Remove bias_pll_cc_clk, bias_pll_nss_noc_clk, bias_pll_ubi_nc_clk nodes from DTS. Because these clocks will be enabled by CMN PLL [1]. Until the CMN PLL driver posted with these clocks set these entries to 0 in the nsscc node. 1: https://lore.kernel.org/lkml/20240827-qcom_ipq_cmnpll-v3-0-8e009cece8b2@quicinc.com/ - Fixed the title arch/arm64/boot/dts/qcom/ipq9574.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 08a82a5cf667..943c5757c36e 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include / { @@ -756,6 +758,27 @@ frame@b128000 { status = "disabled"; }; }; + + nsscc: clock-controller@39b00000 { + compatible = "qcom,ipq9574-nsscc"; + reg = <0x39b00000 0x80000>; + clocks = <&xo_board_clk>, + <0>, + <0>, + <0>, + <&gcc GPLL0_OUT_AUX>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&gcc GCC_NSSCC_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + #interconnect-cells = <1>; + }; }; thermal-zones {