From patchwork Fri Oct 4 08:03:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 833064 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82E3683CD9; Fri, 4 Oct 2024 08:04:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728029080; cv=none; b=gl7pU1Yl/KN0FTU2z4i0DXAI4qk8E8s6ShDpKknusELaRngLIFiwAZ8Os/TsI6AP7PO+TMlmOQWaY2NY7cyyETI2zo7II5f647SM2pyR6eH7FisQxG0kIHvA2upQtRt+WfTdS6p7U8XgYlFBt18FRh6zH4YIYCig4mIjRAuQXJE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728029080; c=relaxed/simple; bh=G0x1r4toyRw3HvpzF9lN1uBbjb74etJTsJ0ke5h5GFQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dvW7Mt7tMzp0eQqA14WulyHvsnV8CL9ZEEQsLcovjGPLi48gERu9HBZKP4bGTRWaz/08mzcR6WJ2aLLNvCENWKmvFSe84H38d1pvsGYYWHEBetaFCDVHF5kNnyf5mfTe0DWFlGm9VoNmcmoYwlqBJuJN3BOBY6K0Hda9Q0Pda98= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=fvNw6Gya; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="fvNw6Gya" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 493HxYUa014164; Fri, 4 Oct 2024 08:04:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Kj5SfIw6yy+K95VuvvevmRrrnelaD+agiQh3W+c+kZ8=; b=fvNw6Gya4djECxSL U15ZFXVHfrxF+oTskjUolnbCpmjjDdCRNGnRAxFwaXK5tng0XsMpDnTJoSU7jIXm 2QUitxYb2Pb3xs278/O9gOUIf91sxGoponHawFYvXe5d2ZGJAZp4xibuPcdTCJZ1 PKlN3jpB/0jTl2g6njZwgS/RSNRYwcus0pFd5lFKqNzMlsP+Ky6pCVBRQRI2llxe EOWHnImhIhpK7aYPJ7ggIn4hx49wprK9mD42RHZWTBC3ejNZNMsSECSokL8QBY+i ws4SSgBzVOb9DW2v9uAgiIH64Wz4kJe0fUKt3vQEpilcI13gEsAdOv8nfUE5cPTR dQqr9g== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42205e1f4d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 04 Oct 2024 08:04:20 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49484JvP022402 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 4 Oct 2024 08:04:19 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 4 Oct 2024 01:04:11 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v6 3/7] clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock Date: Fri, 4 Oct 2024 13:33:28 +0530 Message-ID: <20241004080332.853503-4-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241004080332.853503-1-quic_mmanikan@quicinc.com> References: <20241004080332.853503-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: g5nXW2buJWpntJmiksjsD9o8LcW3ZDBi X-Proofpoint-ORIG-GUID: g5nXW2buJWpntJmiksjsD9o8LcW3ZDBi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 adultscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040057 From: Devi Priya Add support for gpll0_out_aux clock which acts as the parent for certain networking subsystem (nss) clocks. Signed-off-by: Devi Priya Signed-off-by: Manikanta Mylavarapu Reviewed-by: Dmitry Baryshkov --- Changes in V6: - Pick up R-b tag drivers/clk/qcom/gcc-ipq9574.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 645109f75b46..a458d69e1a98 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -108,6 +108,20 @@ static struct clk_alpha_pll_postdiv gpll0 = { }, }; +static struct clk_alpha_pll_postdiv gpll0_out_aux = { + .offset = 0x20000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpll0_out_aux", + .parent_hws = (const struct clk_hw *[]) { + &gpll0_main.clkr.hw + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + static struct clk_alpha_pll gpll4_main = { .offset = 0x22000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], @@ -4222,6 +4236,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, + [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr, }; static const struct qcom_reset_map gcc_ipq9574_resets[] = {