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[88.112.131.206]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5389fd5e333sm259724e87.76.2024.09.27.03.32.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Sep 2024 03:32:16 -0700 (PDT) From: Vladimir Zapolskiy To: Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Jagadeesh Kona Cc: Michael Turquette , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/3] arm64: dts: qcom: sm8550: Change camcc power domain from MMCX to MXC Date: Fri, 27 Sep 2024 13:32:10 +0300 Message-ID: <20240927103212.4154273-2-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240927103212.4154273-1-vladimir.zapolskiy@linaro.org> References: <20240927103212.4154273-1-vladimir.zapolskiy@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Any attempt to enable titan_top_gdsc on SM8550-QRD fails and produces an error message that the gdsc is stuck at 'off' state, this can be easily verified just by setting cci0 status on: cam_cc_titan_top_gdsc status stuck at 'off' WARNING: CPU: 6 PID: 89 at drivers/clk/qcom/gdsc.c:178 gdsc_toggle_logic+0x154/0x168 However if MMCX power domain is replaced by MXC one, it allows to turn titan_top_gdsc on successfully, even if MMCX is remained off according to /sys/kernel/debug/pm_genpd/pm_genpd_summary report. Fixes: e271b59e39a6 ("arm64: dts: qcom: sm8550: Add camera clock controller") Signed-off-by: Vladimir Zapolskiy --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 9dc0ee3eb98f..5c07d1b35615 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2846,7 +2846,7 @@ camcc: clock-controller@ade0000 { <&bi_tcxo_div2>, <&bi_tcxo_ao_div2>, <&sleep_clk>; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd SM8550_MXC>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>;