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[88.112.131.206]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-537a864d937sm156713e87.273.2024.09.24.03.06.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Sep 2024 03:06:19 -0700 (PDT) From: Vladimir Zapolskiy To: Bjorn Andersson , Konrad Dybcio Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 4/9] arm64: dts: qcom: sm8450: don't disable dispcc by default Date: Tue, 24 Sep 2024 13:05:57 +0300 Message-ID: <20240924100602.3813725-5-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240924100602.3813725-1-vladimir.zapolskiy@linaro.org> References: <20240924100602.3813725-1-vladimir.zapolskiy@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable display clock controller for all Qualcomm SM8450 powered boards by default. Signed-off-by: Vladimir Zapolskiy --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 9bafb3b350ff..da378c2ed482 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3435,7 +3435,6 @@ dispcc: clock-controller@af00000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - status = "disabled"; }; pdc: interrupt-controller@b220000 {