| Message ID | 20240924-add_llcc_support_for_qcs615-v1-2-a9f3289760d3@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | soc: qcom: llcc: Add LLCC support for the QCS615 platform | expand |
On 10/6/2024 10:03 AM, Bjorn Andersson wrote: > On Tue, Sep 24, 2024 at 06:07:12PM GMT, Song Xue wrote: >> Add LLCC configuration support for the QCS615 platform. >> >> Signed-off-by: Song Xue <quic_songxue@quicinc.com> >> --- >> drivers/soc/qcom/llcc-qcom.c | 23 +++++++++++++++++++++++ >> 1 file changed, 23 insertions(+) >> >> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c >> index 8fa4ffd3a9b5921d95c20648048dcdfa20dde5db..11507eb3efff101e4f330e7f4282a31aa172369d 100644 >> --- a/drivers/soc/qcom/llcc-qcom.c >> +++ b/drivers/soc/qcom/llcc-qcom.c >> @@ -151,6 +151,13 @@ enum llcc_reg_offset { >> LLCC_COMMON_STATUS0, >> }; >> >> +static const struct llcc_slice_config qcs615_data[] = { >> + { LLCC_CPUSS, 1, 128, 1, 0, 0xF, 0x0, 0, 0, 0, 0, 1, 1 }, > > I accepted Konrad's reformatting of these tables, so please check > linux-next in a couple of days (or the qcom for-next today), update and > resubmit this. > > While doing so, please use lowercase hex digits. > > No other concerns. > > Thanks, > Bjorn > Got it. I will follow Konrad's reformatting and resubmit it. Thanks, Song >> + { LLCC_MDM, 8, 256, 0, 1, 0xF, 0x0, 0, 0, 0, 0, 1, 0 }, >> + { LLCC_GPUHTW, 11, 128, 1, 1, 0xF, 0x0, 0, 0, 0, 0, 1, 0 }, >> + { LLCC_GPU, 12, 128, 1, 0, 0xF, 0x0, 0, 0, 0, 0, 1, 0 }, >> +}; >> + >> static const struct llcc_slice_config sa8775p_data[] = { >> {LLCC_CPUSS, 1, 2048, 1, 0, 0x00FF, 0x0, 0, 0, 0, 1, 1, 0, 0}, >> {LLCC_VIDSC0, 2, 512, 3, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, >> @@ -539,6 +546,16 @@ static const u32 llcc_v2_1_reg_offset[] = { >> [LLCC_COMMON_STATUS0] = 0x0003400c, >> }; >> >> +static const struct qcom_llcc_config qcs615_cfg[] = { >> + { >> + .sct_data = qcs615_data, >> + .size = ARRAY_SIZE(qcs615_data), >> + .need_llcc_cfg = true, >> + .reg_offset = llcc_v1_reg_offset, >> + .edac_reg_offset = &llcc_v1_edac_reg_offset, >> + }, >> +}; >> + >> static const struct qcom_llcc_config qdu1000_cfg[] = { >> { >> .sct_data = qdu1000_data_8ch, >> @@ -721,6 +738,11 @@ static const struct qcom_llcc_config x1e80100_cfg[] = { >> }, >> }; >> >> +static const struct qcom_sct_config qcs615_cfgs = { >> + .llcc_config = qcs615_cfg, >> + .num_config = ARRAY_SIZE(qcs615_cfg), >> +}; >> + >> static const struct qcom_sct_config qdu1000_cfgs = { >> .llcc_config = qdu1000_cfg, >> .num_config = ARRAY_SIZE(qdu1000_cfg), >> @@ -1375,6 +1397,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) >> } >> >> static const struct of_device_id qcom_llcc_of_match[] = { >> + { .compatible = "qcom,qcs615-llcc", .data = &qcs615_cfgs }, >> { .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs}, >> { .compatible = "qcom,sa8775p-llcc", .data = &sa8775p_cfgs }, >> { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs }, >> >> -- >> 2.25.1 >>
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 8fa4ffd3a9b5921d95c20648048dcdfa20dde5db..11507eb3efff101e4f330e7f4282a31aa172369d 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -151,6 +151,13 @@ enum llcc_reg_offset { LLCC_COMMON_STATUS0, }; +static const struct llcc_slice_config qcs615_data[] = { + { LLCC_CPUSS, 1, 128, 1, 0, 0xF, 0x0, 0, 0, 0, 0, 1, 1 }, + { LLCC_MDM, 8, 256, 0, 1, 0xF, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_GPUHTW, 11, 128, 1, 1, 0xF, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_GPU, 12, 128, 1, 0, 0xF, 0x0, 0, 0, 0, 0, 1, 0 }, +}; + static const struct llcc_slice_config sa8775p_data[] = { {LLCC_CPUSS, 1, 2048, 1, 0, 0x00FF, 0x0, 0, 0, 0, 1, 1, 0, 0}, {LLCC_VIDSC0, 2, 512, 3, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, @@ -539,6 +546,16 @@ static const u32 llcc_v2_1_reg_offset[] = { [LLCC_COMMON_STATUS0] = 0x0003400c, }; +static const struct qcom_llcc_config qcs615_cfg[] = { + { + .sct_data = qcs615_data, + .size = ARRAY_SIZE(qcs615_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, +}; + static const struct qcom_llcc_config qdu1000_cfg[] = { { .sct_data = qdu1000_data_8ch, @@ -721,6 +738,11 @@ static const struct qcom_llcc_config x1e80100_cfg[] = { }, }; +static const struct qcom_sct_config qcs615_cfgs = { + .llcc_config = qcs615_cfg, + .num_config = ARRAY_SIZE(qcs615_cfg), +}; + static const struct qcom_sct_config qdu1000_cfgs = { .llcc_config = qdu1000_cfg, .num_config = ARRAY_SIZE(qdu1000_cfg), @@ -1375,6 +1397,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) } static const struct of_device_id qcom_llcc_of_match[] = { + { .compatible = "qcom,qcs615-llcc", .data = &qcs615_cfgs }, { .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs}, { .compatible = "qcom,sa8775p-llcc", .data = &sa8775p_cfgs }, { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
Add LLCC configuration support for the QCS615 platform. Signed-off-by: Song Xue <quic_songxue@quicinc.com> --- drivers/soc/qcom/llcc-qcom.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)