From patchwork Tue Sep 17 20:38:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 829669 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FFE4190067; Tue, 17 Sep 2024 20:39:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726605585; cv=none; b=OLdCf6qTOaTYHpjZU97LcVDg0OjjyvBhIt0TPupobdzNqhFVxE4FoulvjvwJIUIJKI3sf8hYPgEm4x7iTfUL3s0ioogyDD3/OPPqTJDgUICk+6p4PwnZvxGgnf2i6BAG7i4WJhiUxbiZf2r4/XHasKg4+OhF5JM5FaOACvtr1T4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726605585; c=relaxed/simple; bh=bxsKbmm9kkuz1RA3NZIz329WqdshwBhbOvsjnxlwYQQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=dABUpZaYuTVUlOzV9Bq3+y52SeOuFvs5G1X24JuMz/7Wd1lNiAUo9w5AZjon8n3+9aKi4AZu01XKotlSXZ9C5QhRP9DrV0LR5CJi3HE1vgVMPRAnHuo8BQKwrE8i0CduxPAhzPtGNHHrFwdzCUA1ecFybeMmE+MEF3+Pdk9jt4c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=M8PH18MB; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="M8PH18MB" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48HI0fGU019745; Tue, 17 Sep 2024 20:39:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Ksd+tDqDvj1vhxj2bop7NP/KDMWQ/RNWC91hZ84E/ZU=; b=M8PH18MBCzN16awM pqxwH1vjd6HD7QGConQ9ZH2jT6HmvigBBa03NQtow3yK1n8baTQtEJ5MymU/8vCK y76vmi2i+AT2n2HfGyRgI1JHbTuYbeGx0VrTx3LhZvzE+X8RC2SkrQhELYGuhFRn bFpy+fBLym+NXXXF1PBVTA3Tl06MO/xK61UevW9DFtRpx6FCfdaB+E8gxBtk6qto OjFFqQIszDJGHqKZQT6x/nOr/wxdMmi5S+q3vCt8le7J/3u82tQNps/4oo+Zzejz MvPwT29NxPIXwJANR1CukyoP0/n6ntie5k9F+nOYRdpi6KnMVG3MqUZiuYPiu3Yq Lh1KEg== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41n4k0r01j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Sep 2024 20:39:30 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48HKdTr0021688 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Sep 2024 20:39:29 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 17 Sep 2024 13:39:22 -0700 From: Akhil P Oommen Date: Wed, 18 Sep 2024 02:08:43 +0530 Subject: [PATCH 3/3] arm64: dts: qcom: sa8775p: Add gpu and gmu nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240918-a663-gpu-support-v1-3-25fea3f3d64d@quicinc.com> References: <20240918-a663-gpu-support-v1-0-25fea3f3d64d@quicinc.com> In-Reply-To: <20240918-a663-gpu-support-v1-0-25fea3f3d64d@quicinc.com> To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , "Daniel Vetter" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson CC: , , , , , Akhil P Oommen , Puranam V G Tejaswi X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726605543; l=3427; i=quic_akhilpo@quicinc.com; s=20240726; h=from:subject:message-id; bh=YcuLV7CYQ9i9FanWtKsSPESYzGT7pdn0eE2r0GN6uQQ=; b=gssJCgYnTzZ27n0Hej4eUxADMSau8UzE8tUJyB1xtXxRgpRPOOYmXJbsxw50IVbFMTAfSUK7k Zqh+e4j3hb+AenTvxc0xBn6OP9tfh4A3y/p6CDOwGt2lgJ1IZXX3HIq X-Developer-Key: i=quic_akhilpo@quicinc.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ZwSyPe5gLm22YYMlskXsF1kkCiuIYQkp X-Proofpoint-GUID: ZwSyPe5gLm22YYMlskXsF1kkCiuIYQkp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 phishscore=0 spamscore=0 malwarescore=0 bulkscore=0 impostorscore=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409170147 From: Puranam V G Tejaswi Add gpu and gmu nodes for sa8775p based platforms. Signed-off-by: Puranam V G Tejaswi Signed-off-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 8 ++++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 75 ++++++++++++++++++++++++++++++ 2 files changed, 83 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi index 2a6170623ea9..a01e6675c4bb 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -407,6 +407,14 @@ queue3 { }; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sa8775p/a663_zap.mbn"; + }; +}; + &i2c11 { clock-frequency = <400000>; pinctrl-0 = <&qup_i2c11_default>; diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 23f1b2e5e624..12c79135a303 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2824,6 +2824,81 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-663.0", "qcom,adreno"; + reg = <0 0x03d00000 0 0x40000>, + <0 0x03d9e000 0 0x1000>, + <0 0x03d61000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + interrupts = ; + iommus = <&adreno_smmu 0 0xc00>, + <&adreno_smmu 1 0xc00>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "gfx-mem"; + #cooling-cells = <2>; + + status = "disabled"; + + zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-405000000 { + opp-hz = /bits/ 64 <405000000>; + opp-level = ; + opp-peak-kBps = <8368000>; + }; + + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu"; + reg = <0 0x03d6a000 0 0x34000>, + <0 0x3de0000 0 0x10000>, + <0 0x0b290000 0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub", + "smmu_vote"; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", + "gx"; + iommus = <&adreno_smmu 5 0xc00>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sa8775p-gpucc"; reg = <0x0 0x03d90000 0x0 0xa000>;