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Tue, 17 Sep 2024 10:46:33 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 17 Sep 2024 03:46:28 -0700 From: Krishna chaitanya chundru Date: Tue, 17 Sep 2024 16:16:20 +0530 Subject: [PATCH] PCI: qcom: Skip wait for link up if global IRQ handler is present Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240917-remove_wait-v1-1-456d2551bc50@quicinc.com> X-B4-Tracking: v=1; b=H4sIAPtd6WYC/1XMQQ7CIBCF4as0sxYDhKq48h6mMRQGO4sWhYqah ruLTVy4/F/yvgUSRsIEx2aBiJkShamG2DRgBzNdkZGrDZJLxbUQLOIYMl6ehmZmnNpJdXBWew7 1cYvo6bVq5672QGkO8b3iWXzXnyP/nCyYYHrvle9963rXnu4PsjTZrQ0jdKWUD51TOQSoAAAA To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas CC: , , , , , , , , , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726569988; l=3046; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=VwgbqRmMuYTyDjqru++XjKig9TQvq7qY0bPQ4ERYZMg=; b=VsXWHIU4Kh0jK9AgQj+PMMsiGPy6VBUR3XVayM6dnnh0uogoZNFk3R91vilnE/9rWW4squtzq aPS2pbRTq5zDoyBbwMEt3yraga8/KYB/1doPoJBgKi8kvVnBiFXSg6f X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: oKPnwRu_0Z3vgc9B1TSmBpiTvf-nhpCz X-Proofpoint-GUID: oKPnwRu_0Z3vgc9B1TSmBpiTvf-nhpCz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 clxscore=1015 adultscore=0 mlxscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 spamscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=881 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409170077 In cases where a global IRQ handler is present to manage link up interrupts, it may not be necessary to wait for the link to be up during PCI initialization which optimizes the bootup time. Move platform_get_irq_byname_optional() above to set bypass_link_up_wait before dw_pcie_host_init() as this flag is used in this function only. And also as part of the PCIe link up event, update ICC and OPP values. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 3 ++- drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 7 ++++++- 3 files changed, 9 insertions(+), 2 deletions(-) --- base-commit: 9aaeb87ce1e966169a57f53a02ba05b30880ffb8 change-id: 20240911-remove_wait-ad46248dc9f0 Best regards, diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 3e41865c7290..e0ddfaf9f87a 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -531,7 +531,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) } /* Ignore errors, the link may come up later */ - dw_pcie_wait_for_link(pci); + if (!pp->bypass_link_up_wait) + dw_pcie_wait_for_link(pci); bridge->sysdata = pp; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index e518f81ea80c..7fe0e9b1b095 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -348,6 +348,7 @@ struct dw_pcie_rp { bool use_atu_msg; int msg_atu_index; struct resource *msg_res; + bool bypass_link_up_wait; }; struct dw_pcie_ep_ops { diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 88a98be930e3..bcb8c60453ba 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1552,6 +1552,8 @@ static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) pci_lock_rescan_remove(); pci_rescan_bus(pp->bridge->bus); pci_unlock_rescan_remove(); + + qcom_pcie_icc_opp_update(pcie); } else { dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", status); @@ -1686,6 +1688,10 @@ static int qcom_pcie_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pcie); + irq = platform_get_irq_byname_optional(pdev, "global"); + if (irq > 0) + pp->bypass_link_up_wait = true; + ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "cannot initialize host\n"); @@ -1699,7 +1705,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_host_deinit; } - irq = platform_get_irq_byname_optional(pdev, "global"); if (irq > 0) { ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, qcom_pcie_global_irq_thread,