From patchwork Mon Aug 19 22:10:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 820686 Received: from mail-qk1-f176.google.com (mail-qk1-f176.google.com [209.85.222.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2FBF1DF67D; Mon, 19 Aug 2024 22:11:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.222.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724105468; cv=none; b=CsiTrkfGJvTr/SaDUxx1hlaHsSZVoKHsXiTHUd8HWYxp2DwV8De+reTP92OW0foWRyrdNPYifAWSPzkW4qpZPDuCxZK1ukLF9+rYvcNTJJd2irKQ972DPboUdt7e/3cTzXldH79FjicXuTmPTfT8b30KrjS5/jo1OwcIXWYLx1w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724105468; c=relaxed/simple; bh=tnjxV2VvnXns7n2Knjg26+27dYtt61E8TIRYlSlKg+c=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OUzExk/hMblJmkBq49WaXom3/iCBG9ZxVlcAqEVYPueinViToZHj2yTCNCs5r2OLugCzaTIyx376gUUAmBh8LhXr7vC161v1gReIcL+iwUJIdY6peDKwKzoKqtbV3RzdLnu2COyxS3dnJcZjliSmaMKTFK7Ry3d0BqnlVE9cztk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=FQgIXQDK; arc=none smtp.client-ip=209.85.222.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FQgIXQDK" Received: by mail-qk1-f176.google.com with SMTP id af79cd13be357-7a1d3e93cceso557256285a.1; Mon, 19 Aug 2024 15:11:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1724105466; x=1724710266; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2wIngiQeJGUQfKfmpwRGyoAi8JjHIk4mGP79f/O4PBk=; b=FQgIXQDKOyHStgzIDmiODKoWqbPBGVbH4jB64ZzXYiCAJkshaLboVyAFd3uSWdrNXI h8G1iUo9z1c1Z3Bv6ts8leZOO7ABKHCkQGmU913Xx1ZiegCYLvyHJcVCtoKq1WuzZbV3 GFVy3DwlepMqiAoPuXDtPywLKOYZQSiaK8vGf6hyl5s5nn25lpKrC9R5n75Y5B0BmyvG hTNuksXp9DAr2lCMfo9kMV86czjt1Hj/PEezzbI+YibwlzASn1yqm+YxOt83wQ2jfFCH t90T5QUpmCEmys1JHYUZ+ohsjcjdHmnhnJpQHYoHEVRtIjoJcxSa8lmNSvGcccaPoVPc yuzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724105466; x=1724710266; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2wIngiQeJGUQfKfmpwRGyoAi8JjHIk4mGP79f/O4PBk=; b=C1hi+mKDEDam3g3fW8AY4FtFNsdGFbjfbMTTlWWcA87tnGo7QFO1QgfLef54nMi/LF UdP9fnci46NiyKAW90Yyy3BeaE0zI7TgFe72PHFHHEorMbamKBLKCOJbND3sGvjWNWsj N9wBg50z2EDi/4W6NS+b1xi3MDQC84/sp1f8XoRV7T9NWw4WVpkSSmexPS8EfDOCcdqb /tSuWEnodNEigrMWvaXR7PYuD5ThjjDpIbLJ1G46/GHowtKOyMfF9jDknMfFAreCDoBO s6TA4Tpig+swcCr0b/4/a24Nd5b6qT2IsTpbAQHFa+CUaSI0i58fBboxNX7S5Y6yXjAb z0rQ== X-Forwarded-Encrypted: i=1; AJvYcCU53/IUZWOU5Zv2MPvvG/xyX0HOM15sBJ8aO/PUbxwwR0H5TA+CtHPSvxTCxV7gkngrmWYaMPRIyoFYFi0=@vger.kernel.org, AJvYcCUk2WXfrxloNDGgxsGOvmpxA0Yv8WPRqITc0PPf6xDD/746DrSd9HSUtEv7YsJ1O6szSCizJhzO54P2EjiArQ==@vger.kernel.org, AJvYcCUxmiIPIQyTt0gk/FsHo7UW1vGFQ06QygOc/N5jK6wI4XgVrodqzrVLluQTrck3MzzdkPt+OF+1oKEj@vger.kernel.org, AJvYcCWhfKAWCBMZOc3NHjeM67t6whDCvhRJ/DiDW4Ruoa/qx3ZivP0XMaPNx78WMB/Fy15X+go3cxCeh9DY@vger.kernel.org X-Gm-Message-State: AOJu0YzRbDxigTP02t0eBnPE6PgXAp+y0PdJiggNL2w+IyvEWHXt9yM7 qOMQwVHjvYX2OW5iJxbGriv4NcrkGVFz3qTzXNGA40ZAFR7AXRhe X-Google-Smtp-Source: AGHT+IHJoi/5xlmMHu/+zijSosHYThrSInCBRnOQe4GF1m7Fle6wbhuxQ15qxVN8jsnFUWWw3SxFKA== X-Received: by 2002:a05:620a:c4b:b0:795:60ba:76e9 with SMTP id af79cd13be357-7a667aa0bb4mr198408385a.4.1724105465626; Mon, 19 Aug 2024 15:11:05 -0700 (PDT) Received: from localhost ([2607:fea8:52a3:d200:324c:b818:b179:79b]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4536a04e6a6sm44355711cf.59.2024.08.19.15.11.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2024 15:11:05 -0700 (PDT) From: Richard Acayan To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , "Bryan O'Donoghue" , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Richard Acayan , linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-media@vger.kernel.org Subject: [PATCH v3 5/5] arm64: dts: qcom: sdm670: add camss and cci Date: Mon, 19 Aug 2024 18:10:57 -0400 Message-ID: <20240819221051.31489-12-mailingradian@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240819221051.31489-7-mailingradian@gmail.com> References: <20240819221051.31489-7-mailingradian@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the camera subsystem and CCI used to interface with cameras on the Snapdragon 670. Signed-off-by: Richard Acayan Reviewed-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 188 +++++++++++++++++++++++++++ 1 file changed, 188 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index ba93cef33dbb..37bc4fa04286 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -6,6 +6,7 @@ * Copyright (c) 2022, Richard Acayan. All rights reserved. */ +#include #include #include #include @@ -1168,6 +1169,34 @@ tlmm: pinctrl@3400000 { gpio-ranges = <&tlmm 0 0 151>; wakeup-parent = <&pdc>; + cci0_default: cci0-default-state { + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_sleep: cci0-sleep-state { + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_default: cci1-default-state { + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_sleep: cci1-sleep-state { + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + qup_i2c0_default: qup-i2c0-default-state { pins = "gpio0", "gpio1"; function = "qup0"; @@ -1400,6 +1429,165 @@ spmi_bus: spmi@c440000 { #interrupt-cells = <4>; }; + cci: cci@ac4a000 { + compatible = "qcom,sdm670-cci", "qcom,msm8996-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac4a000 0 0x4000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_CLK>; + clock-names = "camnoc_axi", + "soc_ahb", + "cpas_ahb", + "cci"; + + assigned-clocks = <&camcc CAM_CC_CCI_CLK>; + assigned-clock-rates = <37500000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + camss: camera-controller@ac65000 { + compatible = "qcom,sdm670-camss"; + reg = <0 0x0ac65000 0 0x1000>, + <0 0x0ac66000 0 0x1000>, + <0 0x0ac67000 0 0x1000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb3000 0 0x1000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acc4000 0 0x4000>, + <0 0x0acc8000 0 0x1000>; + reg-names = "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "csid0", + "vfe1", + "csid1", + "vfe_lite", + "csid2"; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "csi0", + "csi1", + "csi2", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "gcc_camera_ahb", + "gcc_camera_axi", + "soc_ahb", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe_lite", + "vfe_lite_cphy_rx"; + + iommus = <&apps_smmu 0x808 0x0>, + <&apps_smmu 0x810 0x8>, + <&apps_smmu 0xc08 0x0>, + <&apps_smmu 0xc10 0x8>; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + camss_port0: port@0 { + reg = <0>; + }; + + camss_port1: port@1 { + reg = <1>; + }; + + camss_port2: port@2 { + reg = <2>; + }; + }; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sdm845-camcc"; reg = <0 0x0ad00000 0 0x10000>;