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[86.12.82.21]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-429059714d5sm27198425e9.13.2024.08.07.05.34.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Aug 2024 05:34:45 -0700 (PDT) From: Connor Abbott Date: Wed, 07 Aug 2024 13:34:29 +0100 Subject: [PATCH v2 3/3] drm/msm: Fix CP_BV_DRAW_STATE_ADDR name Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240807-a750-devcoredump-fixes-v2-3-d7483736d26d@gmail.com> References: <20240807-a750-devcoredump-fixes-v2-0-d7483736d26d@gmail.com> In-Reply-To: <20240807-a750-devcoredump-fixes-v2-0-d7483736d26d@gmail.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723034082; l=1121; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=8T4wVzkwSHzii8as2XbKY/C9UUv5Tca7yG03x9E+Etk=; b=wqIDhuEtX7BuG+jv+vjbRVSIMhMfbRqv//dwO6pXsZU7yoCL6B/Ds++kyG+eycDhzvfmU1tH6 XiN3OGqFP0nC/FEfH2WvGXWOcXg0C1j09EJ+Y0051f9aU0voy9B3n89 X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= This was missed because we weren't using the a750-specific indexed regs. Fixes: f3f8207d8aed ("drm/msm: Add devcoredump support for a750") Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h b/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h index 260d66eccfec..9a327d543f27 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h @@ -1303,7 +1303,7 @@ static struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = { REG_A6XX_CP_ROQ_DBG_DATA, 0x00800}, { "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x08000}, - { "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR, + { "CP_BV_DRAW_STATE_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR, REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x00200}, { "CP_BV_ROQ_DBG_ADDR", REG_A7XX_CP_BV_ROQ_DBG_ADDR, REG_A7XX_CP_BV_ROQ_DBG_DATA, 0x00800},