From patchwork Tue Jul 9 09:01:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 811542 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABFD127462; Tue, 9 Jul 2024 09:02:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720515780; cv=none; b=mdeZXI3W0mzAKleiELTj48cHkzm/7VruEg8aRr7hiLY5Qk9/RdMBR9HpB/goGQo1EBNklp2gOGZYzyVMgrnjE/iJ68HaR1f79tfJCWqFpTW/q4KdANbmTmsvQFNIa5C0wOkI+ySMh4Kfl+k2wKt+FHniwv001HESf/wf+JqQDZc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720515780; c=relaxed/simple; bh=NbghBCuv6Z9GqbuZNLOUww8AHwyziSDpjlICfOPy36A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gfjR1ZZS0ge8gtsiQMHewmyMIKNCKZFCi1Qda2pitZ1ALtGEialw/XUCIgQwfjb9u7ebcQnskoIWb7RVDBfQLbYLS4Db/CMOUKreDM8L+s5GbVTmMvfE63LkneQK7tUeK267YgwRoiLCojbDndJvAFkjfU5onZo4ruUlKzYCkoU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=eSQpt7d0; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="eSQpt7d0" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 46936KDv003751; Tue, 9 Jul 2024 09:02:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= b7L/FBiJ5rwG+vtCCzRfyxibTJlnj405qJWswdSeEWc=; b=eSQpt7d0Dtv0YnrE wj1mD/fHmxLEtI6B4N89i6yVxZbJ8PXtmTQHR6I0jR8AQ4z5wEVJJR62brLMldiw 9zZ7H3bm6FhfvaCKo6/9KKcMzh/WbS41gqxJe4N/e0TqGW6jTNxVTeAXdzm1oMuM scJ6KSDTnX+M7Vq4dZz99B4dBXKBEyhi09n8ck4UL4/iNiYnRhiLp7Ewm08Wdwh1 qhmbNs8vozQnHJdjR0maL47jAjFqpE+W2Cs4M3k5DsfH3icA5Fw6wb06dNj5m7Dy 5x2G0mPohHsqaYCDkjif4yEPRRyy+jEVljBDOvbJ8tL6TU49I0+ZbbGrnyQaGo9x dQWOEA== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 408w0r8qqd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Jul 2024 09:02:47 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46992kgQ007930 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 9 Jul 2024 09:02:46 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 9 Jul 2024 02:02:38 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , , , , , CC: Dmitry Baryshkov Subject: [PATCH v5 7/9] clk: qcom: gcc-ipq9574: Add CPR clock definition Date: Tue, 9 Jul 2024 14:31:30 +0530 Message-ID: <20240709090132.117077-8-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240709090132.117077-1-quic_varada@quicinc.com> References: <20240709090132.117077-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: mhpXg8V3v0v7aVE5avSo_gPGt7iRIg7b X-Proofpoint-GUID: mhpXg8V3v0v7aVE5avSo_gPGt7iRIg7b X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-08_15,2024-07-08_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 spamscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407090060 Add the CPR clock definition needed for enabling access to CPR register space. Reviewed-by: Dmitry Baryshkov Signed-off-by: Varadarajan Narayanan --- drivers/clk/qcom/gcc-ipq9574.c | 39 ++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index e1dc74d04ed1..eac557937fd3 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -3994,6 +3994,43 @@ static struct clk_branch gcc_xo_div4_clk = { }, }; +static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { + F(24000000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 rbcpr_clk_src = { + .cmd_rcgr = 0x48044, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_xo_map, + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "rbcpr_clk_src", + .parent_data = gcc_xo_gpll0_gpll4, + .num_parents = ARRAY_SIZE(gcc_xo_map), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_rbcpr_clk = { + .halt_reg = 0x48008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x48008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rbcpr_clk", + .parent_hws = (const struct clk_hw *[]) { + &rbcpr_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_hw *gcc_ipq9574_hws[] = { &gpll0_out_main_div2.hw, &gcc_xo_div4_clk_src.hw, @@ -4219,6 +4256,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, + [GCC_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, + [GCC_RBCPR_CLK] = &gcc_rbcpr_clk.clkr, }; static const struct qcom_reset_map gcc_ipq9574_resets[] = {