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Tue, 18 Jun 2024 07:28:19 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 18 Jun 2024 00:28:12 -0700 From: Jie Gan To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Jinlong Mao , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Song Chai , , , , , , , , , Subject: [PATCH v1 3/3] arm64: dts: qcom: Add CSR and ETR nodes for SA8775p Date: Tue, 18 Jun 2024 15:27:26 +0800 Message-ID: <20240618072726.3767974-4-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618072726.3767974-1-quic_jiegan@quicinc.com> References: <20240618072726.3767974-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: -pXA6eQcHzTx80S9Xf6g5sdzkghNLeBA X-Proofpoint-GUID: -pXA6eQcHzTx80S9Xf6g5sdzkghNLeBA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-18_02,2024-06-17_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 clxscore=1015 mlxlogscore=999 lowpriorityscore=0 phishscore=0 priorityscore=1501 spamscore=0 mlxscore=0 suspectscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406180053 Add CSR and ETR device tree nodes to enable related functions. Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 167 ++++++++++++++++++++++++++ 1 file changed, 167 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 839c6ec0a957..1154d456c239 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -1657,6 +1657,36 @@ ice: crypto@1d88000 { clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; + csr: csr@4001000 { + compatible = "qcom,coresight-csr"; + reg = <0x0 0x4001000 0x0 0x1000>; + reg-names = "csr-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + csr_in0: endpoint { + remote-endpoint = + <&etr0_out>; + }; + }; + + port@1 { + reg = <1>; + csr_in1: endpoint { + remote-endpoint = + <&etr1_out>; + }; + }; + }; + }; + stm: stm@4002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x4002000 0x0 0x1000>, @@ -1860,6 +1890,135 @@ qdss_funnel_in1: endpoint { }; }; + replicator@4046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x4046000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + qdss_rep_out0: endpoint { + remote-endpoint = + <&etr_rep_in>; + }; + }; + }; + + in-ports { + port { + qdss_rep_in: endpoint { + remote-endpoint = + <&swao_rep_out0>; + }; + }; + }; + }; + + tmc_etr: tmc@4048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x4048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04c0 0x00>; + + arm,scatter-gather; + qcom,csr-atid-offset = <0xf8>; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint = + <&csr_in0>; + }; + }; + }; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint = + <&etr_rep_out0>; + }; + }; + }; + }; + + replicator@404e000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x404e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + etr_rep_out0: endpoint { + remote-endpoint = + <&etr0_in>; + }; + }; + + port@1 { + reg = <1>; + etr_rep_out1: endpoint { + remote-endpoint = + <&etr1_in>; + }; + }; + }; + + in-ports { + port { + etr_rep_in: endpoint { + remote-endpoint = + <&qdss_rep_out0>; + }; + }; + }; + }; + + tmc_etr1: tmc@404f000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x404f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04a0 0x40>; + + arm,scatter-gather; + arm,buffer-size = <0x400000>; + qcom,csr-atid-offset = <0x108>; + + out-ports { + port { + etr1_out: endpoint { + remote-endpoint = + <&csr_in1>; + }; + }; + }; + + in-ports { + port { + etr1_in: endpoint { + remote-endpoint = + <&etr_rep_out1>; + }; + }; + }; + }; + funnel@4b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x4b04000 0x0 0x1000>; @@ -1935,6 +2094,14 @@ out-ports { #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + swao_rep_out0: endpoint { + remote-endpoint = + <&qdss_rep_in>; + }; + }; + port@1 { reg = <1>; swao_rep_out1: endpoint {