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[24.150.219.207]) by smtp.gmail.com with ESMTPSA id af79cd13be357-798aaecc004sm432892285a.31.2024.06.17.06.50.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 06:50:05 -0700 (PDT) From: Trevor Gamblin Date: Mon, 17 Jun 2024 09:49:50 -0400 Subject: [PATCH v3 10/41] iio: adc: fsl-imx25-gcq: make use of regmap_clear_bits(), regmap_set_bits() Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240617-review-v3-10-88d1338c4cca@baylibre.com> References: <20240617-review-v3-0-88d1338c4cca@baylibre.com> In-Reply-To: <20240617-review-v3-0-88d1338c4cca@baylibre.com> To: Jonathan Cameron , Lars-Peter Clausen , Dmitry Rokosov , Michael Hennerich , Cosmin Tanislav , Chen-Yu Tsai , Hans de Goede , Ray Jui , Scott Branden , Broadcom internal kernel review list , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Saravanan Sekar , Orson Zhai , Baolin Wang , Chunyan Zhang , Maxime Coquelin , Alexandre Torgue , =?utf-8?q?Nuno_S=C3=A1?= , Linus Walleij , Jean-Baptiste Maneyrol , Crt Mori Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Trevor Gamblin X-Mailer: b4 0.13.0 Instead of using regmap_update_bits() and passing the mask twice, use regmap_set_bits(). Instead of using regmap_update_bits() and passing val = 0, use regmap_clear_bits(). Suggested-by: Uwe Kleine-König Signed-off-by: Trevor Gamblin --- drivers/iio/adc/fsl-imx25-gcq.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/iio/adc/fsl-imx25-gcq.c b/drivers/iio/adc/fsl-imx25-gcq.c index b680690631db..b3f037510e35 100644 --- a/drivers/iio/adc/fsl-imx25-gcq.c +++ b/drivers/iio/adc/fsl-imx25-gcq.c @@ -87,13 +87,13 @@ static irqreturn_t mx25_gcq_irq(int irq, void *data) regmap_read(priv->regs, MX25_ADCQ_SR, &stats); if (stats & MX25_ADCQ_SR_EOQ) { - regmap_update_bits(priv->regs, MX25_ADCQ_MR, - MX25_ADCQ_MR_EOQ_IRQ, MX25_ADCQ_MR_EOQ_IRQ); + regmap_set_bits(priv->regs, MX25_ADCQ_MR, + MX25_ADCQ_MR_EOQ_IRQ); complete(&priv->completed); } /* Disable conversion queue run */ - regmap_update_bits(priv->regs, MX25_ADCQ_CR, MX25_ADCQ_CR_FQS, 0); + regmap_clear_bits(priv->regs, MX25_ADCQ_CR, MX25_ADCQ_CR_FQS); /* Acknowledge all possible irqs */ regmap_write(priv->regs, MX25_ADCQ_SR, MX25_ADCQ_SR_FRR | @@ -115,11 +115,10 @@ static int mx25_gcq_get_raw_value(struct device *dev, regmap_write(priv->regs, MX25_ADCQ_ITEM_7_0, MX25_ADCQ_ITEM(0, chan->channel)); - regmap_update_bits(priv->regs, MX25_ADCQ_MR, MX25_ADCQ_MR_EOQ_IRQ, 0); + regmap_clear_bits(priv->regs, MX25_ADCQ_MR, MX25_ADCQ_MR_EOQ_IRQ); /* Trigger queue for one run */ - regmap_update_bits(priv->regs, MX25_ADCQ_CR, MX25_ADCQ_CR_FQS, - MX25_ADCQ_CR_FQS); + regmap_set_bits(priv->regs, MX25_ADCQ_CR, MX25_ADCQ_CR_FQS); time_left = wait_for_completion_interruptible_timeout( &priv->completed, MX25_GCQ_TIMEOUT); @@ -272,9 +271,8 @@ static int mx25_gcq_setup_cfgs(struct platform_device *pdev, MX25_ADCQ_CFG_REFN_MASK, refp | refn); } - regmap_update_bits(priv->regs, MX25_ADCQ_CR, - MX25_ADCQ_CR_FRST | MX25_ADCQ_CR_QRST, - MX25_ADCQ_CR_FRST | MX25_ADCQ_CR_QRST); + regmap_set_bits(priv->regs, MX25_ADCQ_CR, + MX25_ADCQ_CR_FRST | MX25_ADCQ_CR_QRST); regmap_write(priv->regs, MX25_ADCQ_CR, MX25_ADCQ_CR_PDMSK | MX25_ADCQ_CR_QSM_FQS);