From patchwork Thu May 30 05:56:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 800646 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27FFA142E8F for ; Thu, 30 May 2024 05:56:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717048618; cv=none; b=P/SQ06DrkZWemycKdG87Q+sA9ymctATG0Z4qvWCwYMOeiR/Gq+SpJ2cErln8fO25tc8bavxBzxOLr8fxIlc+nwsvWdldIirNVM9D7e5U5qPVWute03Fc84Pjj2B2emBKzVlT8EBMvP3BoI+uMqIhoAIXmLBGgB4nDtBuB7wEYwA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717048618; c=relaxed/simple; bh=WVT01B++cpJsc5aWz2E9Ktl7ovUMti4jIZvkF51Gf+M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DeWHWuZJLEu3tNLqGYfIphuE5wKtxtfeZI+wUKNiX4TV248x3lAQyANHWEsgv95adoDWi194KQlV32vy/4lQDXhDrpzh+G3avxkRoVNjqGQfx6nC+5ZR3KCBUQ0l+y3UuyQWd1uxbc7CNuOfx9szMa//9Wh5WAp7Q9PmbTTzDV4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=H8iR0Rp8; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="H8iR0Rp8" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-1f44b441b08so4556225ad.0 for ; Wed, 29 May 2024 22:56:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717048616; x=1717653416; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3Q2dQm7nGZxBRKpXC++099T4NGLN3Sf0rMWvCRq/ORE=; b=H8iR0Rp8Z/LLhWPaDONl5v/hQnk+KdaUYJZ+EiUKsNTqmpfbdjQTpjARGoMr5WV+Ci DtdG27cGHwbn/dHwSNcW3K7mUYI2hcbGhhr7Vn7WWeH4XyKcckC2jPcxxMgUpoydqATa /QSFCikJwqC3EafVTRKxJmNGTHxZyD7CqzAfGnhiRSLILZBQqezQSgqOBIJ2AMti+dzA zsJZybwSwV58CNXBhL4G2lz8ByNvl7eYmlbCAdAHg+h3UqiJf8Lu5FlyApK7+EHCYRJc uFrDv5k5Feac6x9XGqM3K2I1YR8M8F1CKh5Ta/sVIhnq9Nfp9faHSrZafeejao3GzYcB +EcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717048616; x=1717653416; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3Q2dQm7nGZxBRKpXC++099T4NGLN3Sf0rMWvCRq/ORE=; b=WMiTfovbC636kAs9wlIgfJ+FtRFYVhK80r62koXQoa5+Hvz95ZNVCelPa1wBJ89RYC 8vqjf7j/CjRtxCmN5DsLi3QvHdQhqeXYdTJZHoTr9nYTauO7AQn3+lP6IrMRZIcyoeQF Pq4Fj/CV/z3osulmY2mXGjNxlNgJWb+idbWoGSI86sY/LrR8cJq/yi+U+MJ6FhLzA41n 7vkjQSITNX3ckCk4hLG05iMYiOODWGzxfLfy67blmXQKZmzo/HbSOPe/96mjSrvKPgIm XpB4Q567/OJOnFOABLd9CfLxeRe1PQtF2pJ74ZiGDW4R9OmDkInkPPKBjBK7Ob2glYKN gtYA== X-Gm-Message-State: AOJu0Yz0tJ1RRj2xObPJZle2RTStJJSXwAkyCd3ZEdugHLxfn2WSSyw4 p13Y0xSMaNEOCRgMglEd8dkIAyQUia54lM7fK9QT6CLXSPlHbTYeY5eZOTu1PTc= X-Google-Smtp-Source: AGHT+IFO/Geqv96DJ2x7VEbic3CPcO41EhCM/kO6eOFtgrS539vWSkBfSlTbuVm2DCcEKokaKBV//g== X-Received: by 2002:a17:903:1d1:b0:1f5:e796:f279 with SMTP id d9443c01a7336-1f6193f880amr12124605ad.9.1717048616304; Wed, 29 May 2024 22:56:56 -0700 (PDT) Received: from [127.0.1.1] ([112.64.61.67]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c75ffc6sm110006705ad.9.2024.05.29.22.56.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 22:56:55 -0700 (PDT) From: Jun Nie Date: Thu, 30 May 2024 13:56:45 +0800 Subject: [PATCH v6 1/6] drm/msm/dpu: fix video mode DSC for DSI Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240530-msm-drm-dsc-dsi-video-upstream-4-v6-1-2ab1d334c657@linaro.org> References: <20240530-msm-drm-dsc-dsi-video-upstream-4-v6-0-2ab1d334c657@linaro.org> In-Reply-To: <20240530-msm-drm-dsc-dsi-video-upstream-4-v6-0-2ab1d334c657@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Jessica Zhang , Vinod Koul Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Jonathan Marek , Neil Armstrong X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717048617; l=3798; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=7/Tbk8+Q7zUBUA35jCKdBQKG2nj1ozoalJhqd4RQMnk=; b=Dhlz3AsXrGGPXqlA2+lGadxOh+L1AjtcGB6npyI0d9ojvc8k/NkO8+/YfRe/IyM/VfF9SJVyd OH/km1k/wQ/DlMtij0zP2N2sJJrUar3jLkRTu/HoShmSfieTWRj/ftB X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= From: Jonathan Marek Add width change in DPU timing for DSC compression case to work with DSI video mode. Signed-off-by: Jonathan Marek Signed-off-by: Jun Nie Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Neil Armstrong # on SM8650-QRD Tested-by: Neil Armstrong # on SM8650-HDK Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 ++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 18 ++++++++++++++++++ 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 119f3ea50a7c..48cef6e79c70 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -564,7 +564,7 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) return (num_dsc > 0) && (num_dsc > intf_count); } -static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) +struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) { struct msm_drm_private *priv = drm_enc->dev->dev_private; struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index 002e89cc1705..2167c46c1a45 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -334,6 +334,14 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( */ unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc); +/** + * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder + * This helper function is used by physical encoder to get DSC config + * used for this encoder. + * @drm_enc: Pointer to encoder structure + */ +struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc); + /** * dpu_encoder_get_drm_fmt - return DRM fourcc format * @phys_enc: Pointer to physical encoder structure diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index ef69c2f408c3..925ec6ada0e1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -11,6 +11,7 @@ #include "dpu_trace.h" #include "disp/msm_disp_snapshot.h" +#include #include #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \ @@ -115,6 +116,23 @@ static void drm_mode_to_intf_timing_params( timing->h_front_porch = timing->h_front_porch >> 1; timing->hsync_pulse_width = timing->hsync_pulse_width >> 1; } + + /* + * for DSI, if compression is enabled, then divide the horizonal active + * timing parameters by compression ratio. bits of 3 components(R/G/B) + * is compressed into bits of 1 pixel. + */ + if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) { + struct drm_dsc_config *dsc = + dpu_encoder_get_dsc_config(phys_enc->parent); + /* + * TODO: replace drm_dsc_get_bpp_int with logic to handle + * fractional part if there is fraction + */ + timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / + (dsc->bits_per_component * 3); + timing->xres = timing->width; + } } static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)