| Message ID | 20240512-typec-fix-sm8250-v4-1-ad153c747a97@linaro.org |
|---|---|
| State | Accepted |
| Commit | d85dc696ca60d04b499d8c3d44040ac54599a0d3 |
| Headers | show |
| Series | arm64: dts: qcom: fix description of the Type-C signals | expand |
On 12/05/2024 00:04, Dmitry Baryshkov wrote: > + minItems: 7 > items: > - const: bi_tcxo > - const: dsi0_phy_pll_out_byteclk > @@ -45,6 +53,12 @@ properties: > - const: dsi1_phy_pll_out_dsiclk > - const: dp_phy_pll_link_clk > - const: dp_phy_pll_vco_div_clk > + - const: edp_phy_pll_link_clk > + - const: edp_phy_pll_vco_div_clk > + - const: dptx1_phy_pll_link_clk > + - const: dptx1_phy_pll_vco_div_clk > + - const: dptx2_phy_pll_link_clk > + - const: dptx2_phy_pll_vco_div_clk > > '#clock-cells': > const: 1 > @@ -68,6 +82,20 @@ properties: > A phandle to an OPP node describing required MMCX performance point. > maxItems: 1 > > +allOf: This goes after required: block (like in example-schema). With this fixed: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 59cc88a52f6b..5831579b572e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -27,6 +27,7 @@ properties: - qcom,sm8350-dispcc clocks: + minItems: 7 items: - description: Board XO source - description: Byte clock from DSI PHY0 @@ -35,8 +36,15 @@ properties: - description: Pixel clock from DSI PHY1 - description: Link clock from DP PHY - description: VCO DIV clock from DP PHY + - description: Link clock from eDP PHY + - description: VCO DIV clock from eDP PHY + - description: Link clock from DP1 PHY + - description: VCO DIV clock from DP1 PHY + - description: Link clock from DP2 PHY + - description: VCO DIV clock from DP2 PHY clock-names: + minItems: 7 items: - const: bi_tcxo - const: dsi0_phy_pll_out_byteclk @@ -45,6 +53,12 @@ properties: - const: dsi1_phy_pll_out_dsiclk - const: dp_phy_pll_link_clk - const: dp_phy_pll_vco_div_clk + - const: edp_phy_pll_link_clk + - const: edp_phy_pll_vco_div_clk + - const: dptx1_phy_pll_link_clk + - const: dptx1_phy_pll_vco_div_clk + - const: dptx2_phy_pll_link_clk + - const: dptx2_phy_pll_vco_div_clk '#clock-cells': const: 1 @@ -68,6 +82,20 @@ properties: A phandle to an OPP node describing required MMCX performance point. maxItems: 1 +allOf: + - if: + not: + properties: + compatible: + contains: + const: qcom,sc8180x-dispcc + then: + properties: + clocks: + maxItems: 7 + clock-names: + maxItems: 7 + required: - compatible - reg
On the affected Qualcomm platforms the display clock controller has additional DP input clocks, describe them in DT schema. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../bindings/clock/qcom,dispcc-sm8x50.yaml | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+)