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[78.88.45.141]) by smtp.gmail.com with ESMTPSA id l6-20020aa7d946000000b005723151e99asm3845314eds.95.2024.04.27.05.01.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Apr 2024 05:01:10 -0700 (PDT) From: Konrad Dybcio Date: Sat, 27 Apr 2024 14:01:07 +0200 Subject: [PATCH] clk: qcom: gcc-sm8450: set OPS_PARENT_ENABLE on gcc_sdcc2_apps_clk_src Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240427-topic-8450sdc2-v1-1-631cbb59e0e5@linaro.org> X-B4-Tracking: v=1; b=H4sIAALpLGYC/x3MQQqAIBBA0avErBPUjKSrRAvTsWajohGBePek5 Vv8X6FgJiywDhUyPlQohg4xDmAvE05k5LpBcqm4kgu7YyLLtJp5cVayyVuPBwrUxkGPUkZP7z/ c9tY+2eDW3WAAAAA= To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Vinod Koul Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714219268; l=1319; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=GSvOEBFXHoGc6KMTfKG8BFzHpyuochW40eZKNzW32JE=; b=q/ojXBP9DGmv83YzSffQUKiOa2EJtP8mw16lIw264BpFw8YFs6+27+zLYcY1F+HD5kXLfSW12 B/uCbTFr764C9gPhETN6FppKXvJ/2yt1q8USA3shSiiagw4Q+5GUkx0 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Similar to how it works on other SoCs, the top frequency of the SDHCI2 core clock is generated by a separate PLL (peculiar design choice) that is not guaranteed to be enabled (why does the clock framework not handle this by default?). Add the CLK_OPS_PARENT_ENABLE flag to make sure we're not muxing the RCG input to a dormant source. Fixes: db0c944ee92b ("clk: qcom: Add clock driver for SM8450") Reported-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm8450.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- base-commit: c0b832517f627ead3388c6f0c74e8ac10ad5774b change-id: 20240427-topic-8450sdc2-3fcfebe1e8ad Best regards, diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index e86c58bc5e48..9a1d48ff22bc 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -935,7 +935,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parent_data_7, .num_parents = ARRAY_SIZE(gcc_parent_data_7), - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, .ops = &clk_rcg2_floor_ops, }, };